[coreboot-gerrit] Patch set updated for coreboot: 6087be0 Intel Baytrail Gold2 and earlier FSP Staying Supported

[York Yang (york.yang@intel.com)]

York Yang (york.yang at intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7335

-gerrit

commit 6087be0edef8da1de17026f48d1d708306736dab
Author: York Yang <york.yang at intel.com>
Date:   Tue Nov 4 17:20:46 2014 -0700

    Intel Baytrail Gold2 and earlier FSP Staying Supported
    
    UPD_DATA_REGION structure has been updated to support Baytrail Gold3
    FSP, but incompatible with previous FSP.  Adjust the offset of those
    changed fields if FSP version is early than Gold3.
    
    Change-Id: Ia77431d31bed424ae25f297df893e45157a288a0
    Signed-off-by: York Yang <york.yang at intel.com>
---
 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 11 +++++++++++
 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h |  4 ++++
 2 files changed, 15 insertions(+)

diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index c4b781a..297ccf9 100755
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -48,6 +48,17 @@ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION   *U
 	VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset  + FspInfo->ImageBase);
 	UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);
 	memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
+
+    /* adjust struct UPD_DATA_REGION content for Gold2 and earlier FSP  */
+    /*  Gold3 FSP changes the UPD_DATA_REGION fields, adjust the struct */
+    /*  content in order to backward compatible with older FSP          */
+    /*                                                                  */
+    /*  ISPEnable and PcdRegionTerminator are following PcdGttSize in   */
+    /*  Gold2 and older FSP                                             */
+    if (FspInfo->ImageRevision < FSP_GOLD3_REV_ID) {
+        *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = UpdData->ISPEnable;
+        *(&(UpdData->PcdGttSize)+sizeof(UINT8)+sizeof(UINT8)) = UpdData->PcdRegionTerminator;
+    }
 }
 
 /* default to just enabling HDMI audio */
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
old mode 100644
new mode 100755
index 1b60398..3861ac1
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2014 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -46,4 +47,7 @@
 #define FSP_IMAGE_ID_DWORD0 0x56594C56	/* 'VLYV' */
 #define FSP_IMAGE_ID_DWORD1 0x30574549	/* 'IEW0' */
 
+/* Revision of the FSP binary   */
+#define FSP_GOLD3_REV_ID    0x00000303
+
 #endif /* CHIPSET_FSP_UTIL_H */