[coreboot-gerrit] Patch set updated for coreboot: 593b6b2 intel/fsp_baytrail: add Gold3 FSP support
York Yang (york.yang@intel.com)
gerrit at coreboot.org
Thu Nov 6 21:18:19 CET 2014
York Yang (york.yang at intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7334
-gerrit
commit 593b6b2a279d5ecc1eb628503597f2589e2a3731
Author: York Yang <york.yang at intel.com>
Date: Tue Nov 4 17:04:37 2014 -0700
intel/fsp_baytrail: add Gold3 FSP support
Baytrail Gold3 FSP adds a couple of parameters in UPD_DATA_REGION
making platform more configurable via devicetree.cb
Update the UPD_DATA_REGION structure and pass settings to FSP
Add Baytrail Gold2 and earlier FSP backward compatible, as Gold3
FSP changes UPD_DATA_REGION struct
Change-Id: Ia2d2d0595328ac771762a84da40697a3b7e900c6
Signed-off-by: York Yang <york.yang at intel.com>
---
src/soc/intel/fsp_baytrail/chip.h | 75 +++++++++++++
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 44 +++++++-
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 4 +
src/vendorcode/intel/fsp/baytrail/include/fspvpd.h | 116 ++++++++++++---------
4 files changed, 189 insertions(+), 50 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h
old mode 100644
new mode 100755
index 7e86862..0e29f89
--- a/src/soc/intel/fsp_baytrail/chip.h
+++ b/src/soc/intel/fsp_baytrail/chip.h
@@ -3,6 +3,7 @@
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2014 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -172,6 +173,80 @@ struct soc_intel_fsp_baytrail_config {
#define LPE_ACPI_MODE_DISABLED 1
#define LPE_ACPI_MODE_ENABLED 2
+ uint32_t SerialDebugPortAddress;
+ #define SERIAL_DEBUG_PORT_ADDR_DEFAULT 0x3F8
+
+ uint8_t SerialDebugPortType;
+ #define SERIAL_DEBUG_PORT_TYPE_NONE 0
+ #define SERIAL_DEBUG_PORT_TYPE_IO 1
+ #define SERIAL_DEBUG_PORT_TYPE_MMIO 2
+
+ uint8_t MrcDebugMsg;
+ #define MRC_DEBUG_MSG_DISABLE 0
+ #define MRC_DEBUG_MSG_ENABLE 1
+
+ uint8_t SccEnablePciMode;
+ #define SCC_PCI_MODE_DISABLE 0
+ #define SCC_PCI_MODE_ENABLE 1
+
+ uint8_t IgdRenderStandby;
+ #define IGD_RENDER_STANDBY_DISABLE 0
+ #define IGD_RENDER_STANDBY_ENABLE 1
+
+ uint8_t TxeUmaEnable;
+ #define TXE_UMA_DISABLE 0
+ #define TXE_UMA_ENABLE 1
+
+ /* Memory down data */
+ uint8_t EnableMemoryDown;
+ #define MEMORY_DOWN_DISABLE 0
+ #define MEMORY_DOWN_ENABLE 1
+
+ uint8_t DRAMSpeed;
+ #define DRAM_SPEED_1333MHZ 2
+
+ uint8_t DRAMType;
+ #define DRAM_TYPE_DDR3L 1
+
+ uint8_t DIMM0Enable;
+ #define DIMM0_ENABLE 1
+
+ uint8_t DIMM1Enable;
+ #define DIMM1_DISABLE 0
+
+ uint8_t DIMMDWidth;
+ #define DIMM_DWIDTH_X8 0
+
+ uint8_t DIMMDensity;
+ #define DIMM_DENSITY_2G_BIT 1
+
+ uint8_t DIMMBusWidth;
+ #define DIMM_BUS_WIDTH_64BIT 3
+
+ uint8_t DIMMSides;
+ #define DIMM_SIDE_1RANK 0
+
+ uint8_t DIMMtCL;
+ #define DIMM_TCL_DEFAULT 9
+
+ uint8_t DIMMtRPtRCD;
+ #define DIMM_TRP_TRCD_DEFAULT 9
+
+ uint8_t DIMMtWR;
+ #define DIMM_TWR_DEFAULT 0x0A
+
+ uint8_t DIMMtWTR;
+ #define DIMM_TWTR_DEFAULT 0x05
+
+ uint8_t DIMMtRRD;
+ #define DIMM_TRPD_DEFAULT 0x04
+
+ uint8_t DIMMtRTP;
+ #define DIMM_TRTP_DEFAULT 0x05
+
+ uint8_t DIMMtFAW;
+ #define DIMM_TFAW_DEFAULT 0x14
+
/* ***** ACPI configuration ***** */
/* Options for these are in src/arch/x86/include/arch/acpi.h */
uint8_t fadt_pm_profile;
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
old mode 100644
new mode 100755
index 82f83a9..a60e8d0
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2014 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -69,7 +70,7 @@ typedef struct soc_intel_fsp_baytrail_config config_t;
*
* @param UpdData Pointer to the UPD Data structure
*/
-static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
+static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData)
{
ROMSTAGE_CONST struct device *dev;
ROMSTAGE_CONST config_t *config;
@@ -146,7 +147,13 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
switch (dev->path.pci.devfn) {
case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */
- UpdData->ISPEnable = dev->enabled;
+ if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) {
+ UpdData->ISPEnable = dev->enabled;
+ } else {
+ /* Gold2 and earlier FSP, */
+ /* ISPEnable is the filed next to PcdGttSize in UPD_DATA_REGION struct */
+ *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled;
+ }
printk(BIOS_DEBUG, "MIPI/ISP:\t\t%s\n",
UpdData->PcdEnableSdio?"Enabled":"Disabled");
break;
@@ -303,6 +310,37 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
printk(BIOS_DEBUG, "Xhci:\t\t\t%s\n",
UpdData->PcdEnableXhci?"Enabled":"Disabled");
+ if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) {
+ /* initiate Gold3 added platform settings, 0 will be passed if not define */
+ UpdData->SerialDebugPortAddress = config->SerialDebugPortAddress;
+ UpdData->SerialDebugPortType = config->SerialDebugPortType;
+ UpdData->PcdMrcDebugMsg = config->MrcDebugMsg;
+ UpdData->PcdSccEnablePciMode = config->SccEnablePciMode;
+ UpdData->IgdRenderStandby = config->IgdRenderStandby;
+ UpdData->TxeUmaEnable = config->TxeUmaEnable;
+ printk(BIOS_INFO, "FSP >= Gold3: set new added FSP parameters\n");
+
+ /* initiate memory down parameters when enabled */
+ if (config->EnableMemoryDown != MEMORY_DOWN_DISABLE) {
+ UpdData->PcdMemoryParameters.EnableMemoryDown = config->EnableMemoryDown;
+ UpdData->PcdMemoryParameters.DRAMSpeed = config->DRAMSpeed;
+ UpdData->PcdMemoryParameters.DRAMType = config->DRAMType;
+ UpdData->PcdMemoryParameters.DIMM0Enable = config->DIMM0Enable;
+ UpdData->PcdMemoryParameters.DIMM1Enable = config->DIMM1Enable;
+ UpdData->PcdMemoryParameters.DIMMDWidth = config->DIMMDWidth;
+ UpdData->PcdMemoryParameters.DIMMDensity = config->DIMMDensity;
+ UpdData->PcdMemoryParameters.DIMMBusWidth = config->DIMMBusWidth;
+ UpdData->PcdMemoryParameters.DIMMSides = config->DIMMSides;
+ UpdData->PcdMemoryParameters.DIMMtCL = config->DIMMtCL;
+ UpdData->PcdMemoryParameters.DIMMtRPtRCD = config->DIMMtRPtRCD;
+ UpdData->PcdMemoryParameters.DIMMtWR = config->DIMMtWR;
+ UpdData->PcdMemoryParameters.DIMMtWTR = config->DIMMtWTR;
+ UpdData->PcdMemoryParameters.DIMMtRRD = config->DIMMtRRD;
+ UpdData->PcdMemoryParameters.DIMMtRTP = config->DIMMtRTP;
+ UpdData->PcdMemoryParameters.DIMMtFAW = config->DIMMtFAW;
+ printk(BIOS_INFO, "Memory Down: Enabled\n");
+ }
+ }
}
/* Set up the Baytrail specific structures for the call into the FSP */
@@ -318,7 +356,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
/* Initialize the UPD Data */
GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
- ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr);
+ ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
pFspInitParams->NvsBufferPtr = NULL;
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
old mode 100644
new mode 100755
index 1b60398..3861ac1
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2014 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -46,4 +47,7 @@
#define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */
#define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */
+/* Revision of the FSP binary */
+#define FSP_GOLD3_REV_ID 0x00000303
+
#endif /* CHIPSET_FSP_UTIL_H */
diff --git a/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h
old mode 100644
new mode 100755
index 1b820a8..b001cdb
--- a/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h
+++ b/src/vendorcode/intel/fsp/baytrail/include/fspvpd.h
@@ -1,6 +1,6 @@
/**
-Copyright (C) 2013, Intel Corporation
+Copyright (C) 2013-2014 Intel Corporation
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -28,56 +28,78 @@ are permitted provided that the following conditions are met:
**/
-/**
-
-This file is auto-generated, please DO NOT modify.
+#ifndef __FSPVPD_H__
+#define __FSPVPD_H__
-**/
+#pragma pack(1)
-#ifndef __VPDHEADER_H__
-#define __VPDHEADER_H__
+typedef struct {
+ UINT8 EnableMemoryDown;
+ UINT8 DRAMSpeed; /* DRAM Speed */
+ UINT8 DRAMType; /* DRAM Type */
+ UINT8 DIMM0Enable; /* DIMM 0 Enable */
+ UINT8 DIMM1Enable; /* DIMM 1 Enable */
+ UINT8 DIMMDWidth; /* DRAM device data width */
+ UINT8 DIMMDensity; /* DRAM device data density */
+ UINT8 DIMMBusWidth; /* DIMM Bus Width */
+ UINT8 DIMMSides; /* Ranks Per DIMM */
+ UINT8 DIMMtCL; /* tCL */
+ UINT8 DIMMtRPtRCD; /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
+ UINT8 DIMMtWR; /* tWR in DRAM clk */
+ UINT8 DIMMtWTR; /* tWTR in DRAM clk */
+ UINT8 DIMMtRRD; /* tRRD in DRAM clk */
+ UINT8 DIMMtRTP; /* tRTP in DRAM clk */
+ UINT8 DIMMtFAW; /* tFAW in DRAM clk */
+} MEMORY_DOWN_DATA;
-#pragma pack(1)
typedef struct _UPD_DATA_REGION {
- UINT64 Signature; /* Offset 0x0000 */
- UINT32 RESERVED1; /* Offset 0x0008 */
- UINT8 Padding0[20]; /* Offset 0x000C */
- UINT16 PcdMrcInitTsegSize; /* Offset 0x0014 */
- UINT16 PcdMrcInitMmioSize; /* Offset 0x0016 */
- UINT8 PcdMrcInitSPDAddr1; /* Offset 0x0018 */
- UINT8 PcdMrcInitSPDAddr2; /* Offset 0x0019 */
- UINT8 PcdeMMCBootMode; /* Offset 0x001B */
- UINT8 PcdEnableSdio; /* Offset 0x001C */
- UINT8 PcdEnableSdcard; /* Offset 0x001D */
- UINT8 PcdEnableHsuart0; /* Offset 0x001E */
- UINT8 PcdEnableHsuart1; /* Offset 0x001F */
- UINT8 PcdEnableSpi; /* Offset 0x0020 */
- UINT8 PcdEnableLan; /* Offset 0x0021 */
- UINT8 PcdEnableSata; /* Offset 0x0023 */
- UINT8 PcdSataMode; /* Offset 0x002E */
- UINT8 PcdEnableAzalia; /* Offset 0x002F */
- UINT32 AzaliaConfigPtr; /* Offset 0x0030 */
- UINT8 PcdEnableXhci; /* Offset 0x0034 */
- UINT8 PcdEnableLpe; /* Offset 0x0029 */
- UINT8 PcdLpssSioEnablePciMode; /* Offset 0x002A */
- UINT8 PcdEnableDma0; /* Offset 0x002B */
- UINT8 PcdEnableDma1; /* Offset 0x002C */
- UINT8 PcdEnableI2C0; /* Offset 0x002D */
- UINT8 PcdEnableI2C1; /* Offset 0x002E */
- UINT8 PcdEnableI2C2; /* Offset 0x002F */
- UINT8 PcdEnableI2C3; /* Offset 0x0030 */
- UINT8 PcdEnableI2C4; /* Offset 0x0031 */
- UINT8 PcdEnableI2C5; /* Offset 0x0032 */
- UINT8 PcdEnableI2C6; /* Offset 0x0033 */
- UINT8 PcdEnablePwm0; /* Offset 0x0034 */
- UINT8 PcdEnablePwm1; /* Offset 0x0035 */
- UINT8 PcdEnableHsi; /* Offset 0x0036 */
- UINT8 PcdIgdDvmt50PreAlloc; /* Offset 0x0043 */
- UINT8 PcdApertureSize; /* Offset 0x0044 */
- UINT8 PcdGttSize; /* Offset 0x0045 */
- UINT8 ISPEnable; /* Offset 0x0046 */
- UINT16 PcdRegionTerminator; /* Offset 0x0047 */
+ UINT64 Signature; /* Offset 0x0000 */
+ UINT32 RESERVED1; /* Offset 0x0008 */
+ UINT8 Padding0[20]; /* Offset 0x000C */
+ UINT16 PcdMrcInitTsegSize; /* Offset 0x0020 */
+ UINT16 PcdMrcInitMmioSize; /* Offset 0x0022 */
+ UINT8 PcdMrcInitSPDAddr1; /* Offset 0x0024 */
+ UINT8 PcdMrcInitSPDAddr2; /* Offset 0x0025 */
+ UINT8 PcdeMMCBootMode; /* Offset 0x0026 */
+ UINT8 PcdEnableSdio; /* Offset 0x0027 */
+ UINT8 PcdEnableSdcard; /* Offset 0x0028 */
+ UINT8 PcdEnableHsuart0; /* Offset 0x0029 */
+ UINT8 PcdEnableHsuart1; /* Offset 0x002A */
+ UINT8 PcdEnableSpi; /* Offset 0x002B */
+ UINT8 PcdEnableLan; /* Offset 0x002C */
+ UINT8 PcdEnableSata; /* Offset 0x002D */
+ UINT8 PcdSataMode; /* Offset 0x002E */
+ UINT8 PcdEnableAzalia; /* Offset 0x002F */
+ UINT32 AzaliaConfigPtr; /* Offset 0x0030 */
+ UINT8 PcdEnableXhci; /* Offset 0x0034 */
+ UINT8 PcdEnableLpe; /* Offset 0x0035 */
+ UINT8 PcdLpssSioEnablePciMode; /* Offset 0x0036 */
+ UINT8 PcdEnableDma0; /* Offset 0x0037 */
+ UINT8 PcdEnableDma1; /* Offset 0x0038 */
+ UINT8 PcdEnableI2C0; /* Offset 0x0039 */
+ UINT8 PcdEnableI2C1; /* Offset 0x003A */
+ UINT8 PcdEnableI2C2; /* Offset 0x003B */
+ UINT8 PcdEnableI2C3; /* Offset 0x003C */
+ UINT8 PcdEnableI2C4; /* Offset 0x003D */
+ UINT8 PcdEnableI2C5; /* Offset 0x003E */
+ UINT8 PcdEnableI2C6; /* Offset 0x003F */
+ UINT8 PcdEnablePwm0; /* Offset 0x0040 */
+ UINT8 PcdEnablePwm1; /* Offset 0x0041 */
+ UINT8 PcdEnableHsi; /* Offset 0x0042 */
+ UINT8 PcdIgdDvmt50PreAlloc; /* Offset 0x0043 */
+ UINT8 PcdApertureSize; /* Offset 0x0044 */
+ UINT8 PcdGttSize; /* Offset 0x0045 */
+ UINT32 SerialDebugPortAddress; /* Offset 0x0046 */
+ UINT8 SerialDebugPortType; /* Offset 0x004A */
+ UINT8 PcdMrcDebugMsg; /* Offset 0x004B */
+ UINT8 ISPEnable; /* Offset 0x004C */
+ UINT8 PcdSccEnablePciMode; /* Offset 0x004D */
+ UINT8 IgdRenderStandby; /* Offset 0x004E */
+ UINT8 TxeUmaEnable; /* Offset 0x004F */
+ UINT8 UnusedUpdSpace1[160]; /* Offset 0x0050 */
+ MEMORY_DOWN_DATA PcdMemoryParameters; /* Offset 0x00F0 */
+ UINT16 PcdRegionTerminator; /* Offset 0x0100 */
} UPD_DATA_REGION;
@@ -86,7 +108,7 @@ typedef struct _VPD_DATA_REGION {
UINT32 PcdImageRevision; /* Offset 0x0008 */
UINT32 PcdUpdRegionOffset; /* Offset 0x000C */
UINT8 Padding0[16]; /* Offset 0x0010 */
- UINT32 RESERVED1; /* Offset 0x0020 */
+ UINT32 PcdFspReservedMemoryLength; /* Offset 0x0020 */
UINT8 PcdPlatformType; /* Offset 0x0024 */
UINT8 PcdEnableSecureBoot; /* Offset 0x0025 */
UINT8 PcdMemoryParameters[16]; /* Offset 0x0026 */
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