[coreboot-gerrit] New patch to review for coreboot: 4daeed9 Hudson: Add support for hiding the USB1.1-only OHCI

[Tobias Diedrich (ranma+coreboot@tdiedrich.de)]

Tobias Diedrich (ranma+coreboot at tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7355

-gerrit

commit 4daeed9c113d11041f12300aeb6821318900d56d
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date:   Sat Nov 8 00:38:33 2014 +0100

    Hudson: Add support for hiding the USB1.1-only OHCI
    
    The hudson chipset has 4 USB controllers, the fourth is USB1.1-only and
    (presumably) not used very often, add support for hiding it.
    On the F2A85M the vendor BIOS is hiding both the USB4 OHCI and the SD
    controller, adjust devicetree.cb accordingly.
    Support for hiding the SD controller already exists, but was not yet
    used in the F2A85M devicetree.cb.
    Includes a small whitespace fix.
    
    Change-Id: I804e7852fd0a6f870dd118b429473cb06ebac9a4
    Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
 src/mainboard/asus/f2a85-m/devicetree.cb  |  7 +++----
 src/southbridge/amd/agesa/hudson/hudson.c | 14 ++++++++++++++
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb
index 9ac5574..40d9c88 100644
--- a/src/mainboard/asus/f2a85-m/devicetree.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree.cb
@@ -32,7 +32,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
 				device pci 0.0 on  end # Root Complex
 				device pci 1.0 on  end # Internal Graphics P2P bridge 0x99XX
 				device pci 1.1 on  end # Internal Multimedia
-				device pci 2.0 on end # PCIE SLOT0 x16 blue
+				device pci 2.0 on  end # PCIE SLOT0 x16 blue
 				device pci 3.0 off end # unused?
 				device pci 4.0 on  end # PCIE 4x black
 				device pci 5.0 off end # unused?
@@ -108,10 +108,9 @@ chip northbridge/amd/agesa/family15tn/root_complex
 					end	#superio/ite/it8728f
 				end	#device pci 14.3 # LPC
 				device pci 14.4 on  end # PCI 0x4384
-				device pci 14.5 on  end # USB 2
+				device pci 14.5 off end # Hide USB4 (USB1.1-only OHCI)
 				device pci 14.6 off end # Gec
-				# SD, make it on so the BAR is assigned (if proper hudson on/off handling is implemented this may go away)
-				device pci 14.7 on end
+				device pci 14.7 off end # Hide unused SD controller
 				device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
 				device pci 15.1 on end # PCIe 1 onboard gigabit
 				device pci 15.2 off end # unused
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index 3b57221..c33dc9b 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -109,6 +109,20 @@ void hudson_enable(device_t dev)
 			pm_write8(0xd3, reg8);
 		}
 		break;
+	case (0x14 << 3) | 5: /* 0:14.5  USB1.1 OHCI (USB4) */
+		if (dev->enabled == 0) {
+			// read the VENDEV ID
+			device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 5));
+			u32 sd_device_id = pci_read_config32( sd_dev, 0) >> 16;
+			u8 reg8;
+			if (sd_device_id == PCI_DEVICE_ID_ATI_SB900_USB_20_5) {
+				/* turn off and remove device 0:14.5 from PCI space */
+				reg8 = pm_read8(0xef);
+				reg8 &= ~(1 << 6);
+				pm_write8(0xef, reg8);
+			}
+		}
+		break;
 	default:
 		break;
 	}