[coreboot-gerrit] Patch set updated for coreboot: 0c0d53b mainboard/asus: Add F2A85-M LE variant to F2A85-M.
Tobias Diedrich (ranma+coreboot@tdiedrich.de)
gerrit at coreboot.org
Sat Nov 8 11:00:15 CET 2014
Tobias Diedrich (ranma+coreboot at tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7356
-gerrit
commit 0c0d53beb3b4530d97bd2987457f019cc36924e2
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date: Sat Nov 8 01:28:33 2014 +0100
mainboard/asus: Add F2A85-M LE variant to F2A85-M.
The F2A85-M LE has less DRAM slots and needs different settings.
Additionally, the audio codec verb table is different.
Disable IMC by default since it is unused on this board (IMC pin-straps are
disabled as well).
Fix a bug in routing.asl.
Change-Id: I0e13c91fc924f4f9eac534fd13d57830654dd0aa
Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
src/mainboard/asus/f2a85-m/BiosCallOuts.c | 18 ++++++++++++++++++
src/mainboard/asus/f2a85-m/Kconfig | 23 +++++++++++++++++++++--
src/mainboard/asus/f2a85-m/acpi/routing.asl | 10 +++++-----
src/mainboard/asus/f2a85-m/buildOpts.c | 6 ++++++
src/mainboard/asus/f2a85-m/devicetree.cb | 5 +++++
5 files changed, 55 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c
index 13bee0c..a08f44c 100644
--- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c
+++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c
@@ -51,6 +51,23 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
* the vendor BIOS.
*/
const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
+#ifdef CONFIG_BOARD_VARIANT_ASUS_F2A85_M_LE
+ {0x11, 0x99430140},
+ {0x12, 0x411111f0},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19850},
+ {0x19, 0x02a19c60},
+ {0x1a, 0x0181305f},
+ {0x1b, 0x02214c20},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4004c601},
+ {0x1e, 0x01456130},
+ {0x1f, 0x411111f0},
+ {0xff, 0xffffffff}
+#else
{0x11, 0x99430140},
{0x12, 0x411111f0},
{0x14, 0x01014010},
@@ -66,6 +83,7 @@ const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
{0x1e, 0x01456130},
{0x1f, 0x411111f0},
{0xff, 0xffffffff}
+#endif
};
static const CODEC_TBL_LIST CodecTableList[] =
diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
index 6dea246..672ab2e 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig
+++ b/src/mainboard/asus/f2a85-m/Kconfig
@@ -33,6 +33,18 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_ITE_IT8728F
select BOARD_ROMSIZE_KB_8192
select GFXUMA
+ select HUDSON_DISABLE_IMC
+
+choice
+ prompt "F2A85-M variant"
+ default BOARD_VARIANT_ASUS_F2A85_M
+
+config BOARD_VARIANT_ASUS_F2A85_M
+ bool "F2A85-M"
+
+config BOARD_VARIANT_ASUS_F2A85_M_LE
+ bool "F2A85-M LE"
+endchoice
choice
prompt "DDR3 memory voltage"
@@ -64,7 +76,8 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
string
- default "F2A85-M"
+ default "F2A85-M" if BOARD_VARIANT_ASUS_F2A85_M
+ default "F2A85-M_LE" if BOARD_VARIANT_ASUS_F2A85_M_LE
config HW_MEM_HOLE_SIZEK
hex
@@ -100,7 +113,13 @@ config ONBOARD_VGA_IS_PRIMARY
config VGA_BIOS_ID
string
- default "1002,9993"
+ default "1002,9993" if BOARD_VARIANT_ASUS_F2A85_M
+ default "1002,9901" if BOARD_VARIANT_ASUS_F2A85_M_LE
+
+config VGA_BIOS_FILE
+ string
+ default "pci1002,9993.rom" if BOARD_VARIANT_ASUS_F2A85_M
+ default "pci1002,9901.rom" if BOARD_VARIANT_ASUS_F2A85_M_LE
config HUDSON_LEGACY_FREE
bool
diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl
index 0685f8d..d2976a6 100644
--- a/src/mainboard/asus/f2a85-m/acpi/routing.asl
+++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl
@@ -138,11 +138,11 @@
/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, 0, 19 },
- /* Bus0, Dev 21 PCIE Bridge */
- Package(){0x0015FFFF, 0, 0, 16 },
- Package(){0x0015FFFF, 1, 0, 17 },
- Package(){0x0015FFFF, 2, 0, 18 },
- Package(){0x0015FFFF, 3, 0, 19 },
+ /* Bus 0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 17 },
+ Package(){0x0015FFFF, 1, 0, 18 },
+ Package(){0x0015FFFF, 2, 0, 19 },
+ Package(){0x0015FFFF, 3, 0, 16 },
})
Name(PS2, Package(){
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index cd1c812..d790473 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -439,8 +439,14 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
// Speicifes the HW RXEN training seed for a channel of a socket
//
+#ifdef CONFIG_BOARD_VARIANT_ASUS_F2A85_M_LE
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+#else
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+#endif
+
/*
TODO: is this OK for DDR3 socket FM2?
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb
index 9ac5574..38aae3e 100644
--- a/src/mainboard/asus/f2a85-m/devicetree.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree.cb
@@ -130,8 +130,13 @@ chip northbridge/amd/agesa/family15tn/root_complex
register "spdAddrLookup" = "
{
+#ifdef CONFIG_BOARD_VARIANT_ASUS_F2A85_M_LE
+ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+#else
{ {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+#endif
}"
end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
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