[coreboot-gerrit] Patch set updated for coreboot: 9785b57 src: Too many terminators '; ; ' at end of stmts, stop Skynet

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7362

-gerrit

commit 9785b576741275264027074bc2b2b2b2a323960e
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sun Nov 9 12:06:19 2014 +1100

    src: Too many terminators ';;' at end of stmts, stop Skynet
    
    Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/google/rambi/mainboard_smi.c  | 2 +-
 src/soc/intel/baytrail/refcode.c            | 2 +-
 src/soc/intel/broadwell/refcode.c           | 2 +-
 src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c | 2 +-
 src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c | 2 +-
 src/vendorcode/amd/cimx/sb800/DISPATCHER.c  | 2 +-
 src/vendorcode/amd/pi/00730F01/Lib/amdlib.c | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c
index f2bb7e9..bd76468 100644
--- a/src/mainboard/google/rambi/mainboard_smi.c
+++ b/src/mainboard/google/rambi/mainboard_smi.c
@@ -139,7 +139,7 @@ int mainboard_smi_apmc(uint8_t apmc)
 		google_chromeec_set_sci_mask(0);
 		/* Clear all pending events */
 		while (google_chromeec_get_event() != 0);
-		google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
+		google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
 		break;
 	}
 	return 0;
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
index 92731bb..e855218 100644
--- a/src/soc/intel/baytrail/refcode.c
+++ b/src/soc/intel/baytrail/refcode.c
@@ -90,7 +90,7 @@ static void cache_refcode(const struct rmod_stage_load *rsl)
 	c->magic = RAMSTAGE_CACHE_MAGIC;
 	c->entry_point = (uint32_t)rsl->entry;
 	c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry);
-	c->size = cbmem_entry_size(rsl->cbmem_entry);;
+	c->size = cbmem_entry_size(rsl->cbmem_entry);
 
 	printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n",
 	       &c->program[0], c->size);
diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c
index 3d2f8b5..a745101 100644
--- a/src/soc/intel/broadwell/refcode.c
+++ b/src/soc/intel/broadwell/refcode.c
@@ -95,7 +95,7 @@ static void cache_refcode(const struct rmod_stage_load *rsl)
 	c->magic = RAMSTAGE_CACHE_MAGIC;
 	c->entry_point = (uint32_t)rsl->entry;
 	c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry);
-	c->size = cbmem_entry_size(rsl->cbmem_entry);;
+	c->size = cbmem_entry_size(rsl->cbmem_entry);
 
 	printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n",
 	       &c->program[0], c->size);
diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
index 9646e6d..a2c424a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
@@ -837,7 +837,7 @@ LibAmdPciWrite (
       LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
     }
     //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
-    //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
+    //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
     //printk(BIOS_DEBUG, "LibAmdPciWrite\n");
   } else {
     // Setup the MMIO address
diff --git a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
index 99a28b1..d0e66b9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
@@ -842,7 +842,7 @@ LibAmdPciWrite (
       LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
     }
     //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
-    //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
+    //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
     //printk(BIOS_DEBUG, "LibAmdPciWrite\n");
   } else {
     // Setup the MMIO address
diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
index d3a6c3a..84bbccb 100644
--- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
+++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
@@ -159,7 +159,7 @@ AmdSbDispatcher (
   }
 
   if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
-    sbECfancontrolservice((AMDSBCFG*)pConfig);;
+    sbECfancontrolservice((AMDSBCFG*)pConfig);
   }
 #endif
   return Status;
diff --git a/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c b/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c
index 54e0d77..f2e6b91 100644
--- a/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c
+++ b/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c
@@ -865,7 +865,7 @@ LibAmdPciWrite (
       LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
     }
     //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
-    //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
+    //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
     //printk(BIOS_DEBUG, "LibAmdPciWrite\n");
   } else {
     // Setup the MMIO address