[coreboot-gerrit] New patch to review for coreboot: 8d8f7be AMD chipsets: Keep decode of serial port on in LegacyFree mode.

[Tobias Diedrich (ranma+coreboot@tdiedrich.de)]

Tobias Diedrich (ranma+coreboot at tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7380

-gerrit

commit 8d8f7beab9b9645dfac25f9c34a9aaefd56c507d
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date:   Sun Nov 9 20:07:23 2014 +0100

    AMD chipsets: Keep decode of serial port on in LegacyFree mode.
    
    Even if a board is nominally legacy-free, it's useful to be able to just
    connect a serial port to the LPC bus for debugging.
    
    Change-Id: If6a2fd78d60a39dc25c515e7be16ec0af7ea315f
    Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
 .../agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c   | 3 ++-
 .../agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c   | 3 ++-
 src/vendorcode/amd/cimx/sb700/SBPOR.c                                  | 3 ++-
 src/vendorcode/amd/cimx/sb800/SBPOR.c                                  | 3 ++-
 src/vendorcode/amd/cimx/sb900/SbPor.c                                  | 3 ++-
 5 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
index 36259d3..f16aba2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
@@ -116,7 +116,8 @@ FchInitResetLpcProgram (
   }
 
   if ( LocalCfgPtr->LegacyFree ) {
-    RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0x0003C000, StdHeader);
+    // Keep decode of 0x3f8 (bit 6) on for early debug console.
+    RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0x0003C040, StdHeader);
   } else {
     RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0xFF03FFD5, StdHeader);
   }
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
index ab71bb9..b2a43cd 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
@@ -138,7 +138,8 @@ FchInitResetLpcProgram (
     RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGD0 + 1, AccessWidth8, 0xBF, 0, StdHeader);
   }
   if ( LocalCfgPtr->LegacyFree ) {
-    RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0x0003C000, StdHeader);
+    // Keep decode of 0x3f8 (bit 6) on for early debug console.
+    RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0x0003C040, StdHeader);
   } else {
     RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0xFF03FFD5, StdHeader);
   }
diff --git a/src/vendorcode/amd/cimx/sb700/SBPOR.c b/src/vendorcode/amd/cimx/sb700/SBPOR.c
index 6c5740b..7745d99 100644
--- a/src/vendorcode/amd/cimx/sb700/SBPOR.c
+++ b/src/vendorcode/amd/cimx/sb700/SBPOR.c
@@ -292,7 +292,8 @@ void  sbPowerOnInit (AMDSBCFG *pConfig){
   }
 
   if  (pBuildOptPtr->LegacyFree)        //if LEGACY FREE system
-    RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+    // Keep decode of 0x3f8 (bit 6) on for early debug console.
+    RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C040);
   else
     RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
 
diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c
index 048850d..0c51cbd 100644
--- a/src/vendorcode/amd/cimx/sb800/SBPOR.c
+++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c
@@ -313,7 +313,8 @@ sbPowerOnInit (
   }
 
   if ( pConfig->BuildParameters.LegacyFree ) {
-    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+    // Keep decode of 0x3f8 (bit 6) on for early debug console.
+    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C040);
   } else {
     RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
   }
diff --git a/src/vendorcode/amd/cimx/sb900/SbPor.c b/src/vendorcode/amd/cimx/sb900/SbPor.c
index 90e878e..ac4e2ef 100644
--- a/src/vendorcode/amd/cimx/sb900/SbPor.c
+++ b/src/vendorcode/amd/cimx/sb900/SbPor.c
@@ -355,7 +355,8 @@ sbPowerOnInit (
   }
 
   if ( pConfig->BuildParameters.LegacyFree ) {
-    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+    // Keep decode of 0x3f8 (bit 6) on for early debug console.
+    RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C040);
   } else {
     RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
   }