[coreboot-gerrit] New patch to review for coreboot: adaf4b0 asus/f2a85-m: Disable SD controller

[Tobias Diedrich (ranma+coreboot@tdiedrich.de)]

Tobias Diedrich (ranma+coreboot at tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7383

-gerrit

commit adaf4b082027a54347cee277197c82f0d729865d
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date:   Sun Nov 9 20:16:04 2014 +0100

    asus/f2a85-m: Disable SD controller
    
    The hudson handling alluded to in the original comment was implemented in
    commit ea90963666af1ba49d524c46c9d3257f9438e6c4, use it to disable the
    SD controller so it doesn't show up in lspci.
    
    Change-Id: Ib2ba79a11af06c6765dcad4070232a8a7c6d2751
    Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
 src/mainboard/asus/f2a85-m/devicetree.cb | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb
index 9ac5574..0a79dbe 100644
--- a/src/mainboard/asus/f2a85-m/devicetree.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree.cb
@@ -110,8 +110,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
 				device pci 14.4 on  end # PCI 0x4384
 				device pci 14.5 on  end # USB 2
 				device pci 14.6 off end # Gec
-				# SD, make it on so the BAR is assigned (if proper hudson on/off handling is implemented this may go away)
-				device pci 14.7 on end
+				device pci 14.7 off end # SD
 				device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
 				device pci 15.1 on end # PCIe 1 onboard gigabit
 				device pci 15.2 off end # unused