[coreboot-gerrit] Patch set updated for coreboot: 1eba7dc mainboard/pcengines/apu1c: Add support for pcengines apu1c board.
Tobias Diedrich (ranma+coreboot@tdiedrich.de)
gerrit at coreboot.org
Tue Nov 11 00:09:02 CET 2014
Tobias Diedrich (ranma+coreboot at tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7386
-gerrit
commit 1eba7dc5af06b5f87873386bbbe811ce9086b6e8
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date: Sun Nov 9 20:59:26 2014 +0100
mainboard/pcengines/apu1c: Add support for pcengines apu1c board.
This board is already running coreboot, but the source is not freely available
for download (I mailed the mentioned support page a few days ago, but didn't
get an answer).
http://www.pcengines.ch/apu1c.htm
Based on ASROCK E350M1 and Gizmo Board files.
It boots Linux, Serial port, SATA, USB, Network and PCIe slots work.
Remaining issues:
Needs some more cleanup.
Change-Id: I1f6603020264874c16a56a9f9b19f42574568c31
Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
src/mainboard/pcengines/Kconfig | 3 +
src/mainboard/pcengines/apu1c/BiosCallOuts.c | 72 +++
.../pcengines/apu1c/HYNIX-H5TQ2G83CFR.spd.hex | 250 ++++++++
.../pcengines/apu1c/HYNIX-H5TQ4G83MFR.spd.hex | 252 +++++++++
src/mainboard/pcengines/apu1c/Kconfig | 88 +++
src/mainboard/pcengines/apu1c/Makefile.inc | 56 ++
src/mainboard/pcengines/apu1c/OptionsIds.h | 66 +++
src/mainboard/pcengines/apu1c/PlatformGnbPcie.c | 152 +++++
.../pcengines/apu1c/PlatformGnbPcieComplex.h | 72 +++
src/mainboard/pcengines/apu1c/acpi/gpe.asl | 83 +++
src/mainboard/pcengines/apu1c/acpi/mainboard.asl | 67 +++
src/mainboard/pcengines/apu1c/acpi/routing.asl | 407 +++++++++++++
src/mainboard/pcengines/apu1c/acpi/sata.asl | 149 +++++
src/mainboard/pcengines/apu1c/acpi/sleep.asl | 120 ++++
src/mainboard/pcengines/apu1c/acpi/smbus.asl | 113 ++++
src/mainboard/pcengines/apu1c/acpi/superio.asl | 20 +
src/mainboard/pcengines/apu1c/acpi/thermal.asl | 21 +
src/mainboard/pcengines/apu1c/acpi/usb_oc.asl | 174 ++++++
src/mainboard/pcengines/apu1c/acpi_tables.c | 267 +++++++++
src/mainboard/pcengines/apu1c/agesawrapper.c | 628 +++++++++++++++++++++
src/mainboard/pcengines/apu1c/agesawrapper.h | 60 ++
src/mainboard/pcengines/apu1c/board_info.txt | 6 +
src/mainboard/pcengines/apu1c/buildOpts.c | 476 ++++++++++++++++
src/mainboard/pcengines/apu1c/cmos.layout | 116 ++++
src/mainboard/pcengines/apu1c/devicetree.cb | 81 +++
src/mainboard/pcengines/apu1c/dsdt.asl | 63 +++
src/mainboard/pcengines/apu1c/irq_tables.c | 116 ++++
src/mainboard/pcengines/apu1c/mainboard.c | 69 +++
src/mainboard/pcengines/apu1c/mptable.c | 154 +++++
src/mainboard/pcengines/apu1c/platform_cfg.h | 233 ++++++++
src/mainboard/pcengines/apu1c/romstage.c | 177 ++++++
31 files changed, 4611 insertions(+)
diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig
index 9fb477b..f911d24 100644
--- a/src/mainboard/pcengines/Kconfig
+++ b/src/mainboard/pcengines/Kconfig
@@ -11,6 +11,8 @@ config BOARD_PCENGINES_ALIX2D
bool "ALIX.2D2 or 2D3"
config BOARD_PCENGINES_ALIX6
bool "ALIX.6"
+config BOARD_PCENGINES_APU1C
+ bool "APU1C"
endchoice
@@ -18,6 +20,7 @@ source "src/mainboard/pcengines/alix1c/Kconfig"
source "src/mainboard/pcengines/alix2c/Kconfig"
source "src/mainboard/pcengines/alix2d/Kconfig"
source "src/mainboard/pcengines/alix6/Kconfig"
+source "src/mainboard/pcengines/apu1c/Kconfig"
config MAINBOARD_VENDOR
string
diff --git a/src/mainboard/pcengines/apu1c/BiosCallOuts.c b/src/mainboard/pcengines/apu1c/BiosCallOuts.c
new file mode 100755
index 0000000..c54d58a
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/BiosCallOuts.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "SB800.h"
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <southbridge/amd/cimx/sb800/gpio_oem.h>
+#include <stdlib.h>
+#include <spd_cache.h>
+
+static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+static AGESA_STATUS board_ReadSpdFromCbfs (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
+ {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
+ {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD, board_ReadSpdFromCbfs },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },
+ {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/* Call the host environment interface to provide a user hook opportunity. */
+static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ // Unlike AMD/Inagua, this board is unable to vary the RAM voltage.
+ // Make sure the right speed settings are selected.
+ ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
+ return AGESA_SUCCESS;
+}
+
+static AGESA_STATUS board_ReadSpdFromCbfs (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+#ifdef __PRE_RAM__
+ AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+ int spd_idx = FCH_GPIO(16) & 0x80 ? 1 : 0;
+ printk(BIOS_INFO, "Selecting spd image %d for RAM size %dGB\n",
+ spd_idx, spd_idx ? 4 : 2);
+
+ if (read_spd_from_cbfs((u8*)info->Buffer, spd_idx) < 0)
+ // read_spd_from_cbfs already prints an error message.
+ return AGESA_FATAL;
+#endif
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/mainboard/pcengines/apu1c/HYNIX-H5TQ2G83CFR.spd.hex b/src/mainboard/pcengines/apu1c/HYNIX-H5TQ2G83CFR.spd.hex
new file mode 100644
index 0000000..2755ddc
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/HYNIX-H5TQ2G83CFR.spd.hex
@@ -0,0 +1,250 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+# HYNIX-H5TQ2G83CFR
+
+# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 125
+11
+
+# 1 SPD Revision -
+# 0x10 = Revision 1.0
+10
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[7:4]: reserved
+03
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+03
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[7:6]: reserved
+19
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 1 = 8 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+01
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[7:5]: reserved
+03
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x01 divisor
+# bits[7:4]: 0x01 dividend
+# 1 / 1 = 1.0 ps
+11
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 11 - 5 are supported
+7E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333
+6C
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 13.5ns - DDR3-1333
+6C
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x30 = 6ns
+30
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns - DDR3-1333
+6C
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x28C = 49.5ns - DDR3-1333
+8C
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+00 05
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
+00 F0
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 1 = DLL Off mode supported
+83
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 1 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+05
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 2 = Signal Loading
+# bits[3:2]: reserved
+# bits[6:4]: 4 = Die count
+# bit7 : 0 = Standard Monolithic DRAM Device
+42
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00 00 00 00 00
+
+# 39 (reserved)
+00
+
+# 40 - 47 (reserved)
+00 00 00 00 00 00 00 00
+
+# 48 - 55 (reserved)
+00 00 00 00 00 00 00 00
+
+# 56 - 59 (reserved)
+00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+00
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 71 (reserved)
+00 00 00 00 00 00 00 00
+
+# 72 - 79 (reserved)
+00 00 00 00 00 00 00 00
+
+# 80 - 87 (reserved)
+00 00 00 00 00 00 00 00
+
+# 88 - 95 (reserved)
+00 00 00 00 00 00 00 00
+
+# 96 - 103 (reserved)
+00 00 00 00 00 00 00 00
+
+# 104 - 111 (reserved)
+00 00 00 00 00 00 00 00
+
+# 112 - 116 (reserved)
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x0001 = AMD
+00 01
+
+# 119 Module ID: Module Manufacturing Location - oem specified
+00
+
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x13 = 2013
+# 121 Module ID: Module Manufacture week
+# 0x12 = 12th week
+13 12
+
+# 122 - 125: Module Serial Number
+53 41 47 45
+
+# 126 - 127: Cyclical Redundancy Code
+84 53
diff --git a/src/mainboard/pcengines/apu1c/HYNIX-H5TQ4G83MFR.spd.hex b/src/mainboard/pcengines/apu1c/HYNIX-H5TQ4G83MFR.spd.hex
new file mode 100644
index 0000000..fbc2f86
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/HYNIX-H5TQ4G83MFR.spd.hex
@@ -0,0 +1,252 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+# HYNIX-H5TQ4G83MFR
+
+# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 125
+11
+
+# 1 SPD Revision -
+# 0x10 = Revision 1.0
+10
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[7:4]: reserved
+03
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+04
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[5:3]: 4 = 16 Row Address Bits
+# bits[7:6]: reserved
+21
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 1 = 8 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+01
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[7:5]: reserved
+03
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x01 divisor
+# bits[7:4]: 0x01 dividend
+# 1 / 1 = 1.0 ps
+11
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 11 - 5 are supported
+7E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333
+6C
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 13.5ns - DDR3-1333
+6C
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x30 = 6ns
+30
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns - DDR3-1333
+6C
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x28C = 49.5ns - DDR3-1333
+8C
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+00 05
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
+00 F0
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 1 = DLL Off mode supported
+83
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 1 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+05
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 2 = Signal Loading
+# bits[3:2]: reserved
+# bits[6:4]: 4 = Die count
+# bit7 : 0 = Standard Monolithic DRAM Device
+42
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00 00 00 00 00
+
+# 39 (reserved)
+00
+
+# 40 - 47 (reserved)
+00 00 00 00 00 00 00 00
+
+# 48 - 55 (reserved)
+00 00 00 00 00 00 00 00
+
+# 56 - 59 (reserved)
+00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+00
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 71 (reserved)
+00 00 00 00 00 00 00 00
+
+# 72 - 79 (reserved)
+00 00 00 00 00 00 00 00
+
+# 80 - 87 (reserved)
+00 00 00 00 00 00 00 00
+
+# 88 - 95 (reserved)
+00 00 00 00 00 00 00 00
+
+# 96 - 103 (reserved)
+00 00 00 00 00 00 00 00
+
+# 104 - 111 (reserved)
+00 00 00 00 00 00 00 00
+
+# 112 - 116 (reserved)
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x0001 = AMD
+00 01
+
+# 119 Module ID: Module Manufacturing Location - oem specified
+00
+
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x13 = 2013
+# 121 Module ID: Module Manufacture week
+# 0x12 = 12th week
+13 12
+
+# 122 - 125: Module Serial Number
+53 41 47 45
+
+# 126 - 127: Cyclical Redundancy Code
+c0 d8
diff --git a/src/mainboard/pcengines/apu1c/Kconfig b/src/mainboard/pcengines/apu1c/Kconfig
new file mode 100644
index 0000000..5cbe5fd
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/Kconfig
@@ -0,0 +1,88 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+if BOARD_PCENGINES_APU1C
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_AGESA_FAMILY14
+ select NORTHBRIDGE_AMD_AGESA_FAMILY14
+ select SOUTHBRIDGE_AMD_CIMX_SB800
+ select SUPERIO_NUVOTON_NCT5104D
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_2048
+ select SPD_CACHE
+
+config MAINBOARD_DIR
+ string
+ default pcengines/apu1c
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "APU"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 2
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config RAMTOP
+ hex
+ default 0x1000000
+
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
+config RAMBASE
+ hex
+ default 0x200000
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS
+ bool
+ default n
+
+config VGA_BIOS_ID
+ string
+ default "1002,9802"
+
+config DRIVERS_PS2_KEYBOARD
+ bool
+ default n
+
+endif # BOARD_PCENGINES_APU1C
diff --git a/src/mainboard/pcengines/apu1c/Makefile.inc b/src/mainboard/pcengines/apu1c/Makefile.inc
new file mode 100755
index 0000000..fb17c82
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/Makefile.inc
@@ -0,0 +1,56 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2013 Sage Electronic Engineering, LLC
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+ifeq ($(CONFIG_AHCI_BIOS),y)
+stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
+cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
+pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
+pci$(stripped_ahcibios_id).rom-type := optionrom
+endif
+
+romstage-y += buildOpts.c
+romstage-y += agesawrapper.c
+romstage-y += BiosCallOuts.c
+romstage-y += PlatformGnbPcie.c
+
+ramstage-y += buildOpts.c
+ramstage-y += agesawrapper.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += PlatformGnbPcie.c
+
+## DIMM SPD for on-board memory
+SPD_BIN = $(obj)/spd.bin
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES = HYNIX-H5TQ2G83CFR HYNIX-H5TQ4G83MFR
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do /bin/echo -e -n "\\x$$c"; \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := 0xab
diff --git a/src/mainboard/pcengines/apu1c/OptionsIds.h b/src/mainboard/pcengines/apu1c/OptionsIds.h
new file mode 100755
index 0000000..600753c
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/OptionsIds.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/pcengines/apu1c/PlatformGnbPcie.c b/src/mainboard/pcengines/apu1c/PlatformGnbPcie.c
new file mode 100755
index 0000000..eefd27f
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/PlatformGnbPcie.c
@@ -0,0 +1,152 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+
+#include <string.h>
+
+#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] **PeiServices
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ )
+{
+ AGESA_STATUS Status;
+ VOID *BrazosPcieComplexListPtr;
+ VOID *BrazosPciePortPtr;
+ VOID *BrazosPcieDdiPtr;
+
+ ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+PCIe_PORT_DESCRIPTOR PortList [] = {
+ // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
+ },
+ #if 1
+ // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0)
+ },
+ // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0)
+ },
+ // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
+ },
+ #endif
+ // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+ {
+ DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+ }
+};
+
+PCIe_DDI_DESCRIPTOR DdiList [] = {
+ // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+ {
+ 0, //Descriptor flags
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+ //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+ {ConnectorTypeDP, Aux1, Hdp1}
+ },
+ // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+ {
+ DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+ //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+ {ConnectorTypeDP, Aux2, Hdp2}
+ }
+};
+
+PCIe_COMPLEX_DESCRIPTOR Brazos = {
+ DESCRIPTOR_TERMINATE_LIST,
+ 0,
+ &PortList[0],
+ &DdiList[0]
+};
+
+ // GNB PCIe topology Porting
+
+ //
+ // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+ //
+ AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
+
+ AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+ AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+ Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+ if ( Status!= AGESA_SUCCESS) {
+ // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+ ASSERT(FALSE);
+ return;
+ }
+
+ BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+ AllocHeapParams.BufferPtr += sizeof(Brazos);
+ BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+
+ AllocHeapParams.BufferPtr += sizeof(PortList);
+ BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+ memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
+ memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
+ memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
+
+
+ ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
+ ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+
+ InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+ InitEarly->GnbConfig.PsppPolicy = 0;
+}
diff --git a/src/mainboard/pcengines/apu1c/PlatformGnbPcieComplex.h b/src/mainboard/pcengines/apu1c/PlatformGnbPcieComplex.h
new file mode 100755
index 0000000..5efcd7d
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/PlatformGnbPcieComplex.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
+#define _PLATFORM_GNB_PCIE_COMPLEX_H
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+//GNB GPP Port4
+#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port5
+#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port6
+#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port7
+#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port8
+#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ );
+
+#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/pcengines/apu1c/acpi/gpe.asl b/src/mainboard/pcengines/apu1c/acpi/gpe.asl
new file mode 100644
index 0000000..37e20fb
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/acpi/gpe.asl
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+} /* End Scope GPE */
+
+/* Contains the GPEs for USB overcurrent */
+#include "usb_oc.asl"
diff --git a/src/mainboard/pcengines/apu1c/acpi/mainboard.asl b/src/mainboard/pcengines/apu1c/acpi/mainboard.asl
new file mode 100644
index 0000000..1f532cf
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/acpi/mainboard.asl
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Data to be patched by the BIOS during POST */
+/* FIXME the patching is not done yet! */
+/* Memory related values */
+Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0) /* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+/* Some global data */
+Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones) /* Assume nothing */
+Name(PMOD, One) /* Assume APIC */
+
+Scope(\_SB) {
+ Method(OSFL, 0){
+
+ if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
+
+ if(CondRefOf(\_OSI,Local1))
+ {
+ Store(1, OSVR) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSVR)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSVR) /* Linux */
+ } Else {
+ Store(4, OSVR) /* Gotta be WinCE */
+ }
+ }
+ Return(OSVR)
+ }
+}
+
+Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+} /* End Scope SI */
diff --git a/src/mainboard/pcengines/apu1c/acpi/routing.asl b/src/mainboard/pcengines/apu1c/acpi/routing.asl
new file mode 100755
index 0000000..98ad439
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/acpi/routing.asl
@@ -0,0 +1,407 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - RS780 Host Controller */
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+ Package(){0x0001FFFF, 0, INTC, 0 },
+ Package(){0x0001FFFF, 1, INTD, 0 },
+ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+ Package(){0x0003FFFF, 0, INTD, 0 },
+ Package(){0x0003FFFF, 1, INTA, 0 },
+ Package(){0x0003FFFF, 2, INTB, 0 },
+ Package(){0x0003FFFF, 3, INTC, 0 },
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){0x0005FFFF, 0, INTB, 0 },
+ Package(){0x0005FFFF, 1, INTC, 0 },
+ Package(){0x0005FFFF, 2, INTD, 0 },
+ Package(){0x0005FFFF, 3, INTA, 0 },
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ Package(){0x0006FFFF, 0, INTC, 0 },
+ Package(){0x0006FFFF, 1, INTD, 0 },
+ Package(){0x0006FFFF, 2, INTA, 0 },
+ Package(){0x0006FFFF, 3, INTB, 0 },
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ Package(){0x0007FFFF, 0, INTD, 0 },
+ Package(){0x0007FFFF, 1, INTA, 0 },
+ Package(){0x0007FFFF, 2, INTB, 0 },
+ Package(){0x0007FFFF, 3, INTC, 0 },
+
+ Package(){0x0009FFFF, 0, INTB, 0 },
+ Package(){0x0009FFFF, 1, INTC, 0 },
+ Package(){0x0009FFFF, 2, INTD, 0 },
+ Package(){0x0009FFFF, 3, INTA, 0 },
+
+ Package(){0x000AFFFF, 0, INTC, 0 },
+ Package(){0x000AFFFF, 1, INTD, 0 },
+ Package(){0x000AFFFF, 2, INTA, 0 },
+ Package(){0x000AFFFF, 3, INTB, 0 },
+
+ Package(){0x000BFFFF, 0, INTD, 0 },
+ Package(){0x000BFFFF, 1, INTA, 0 },
+ Package(){0x000BFFFF, 2, INTB, 0 },
+ Package(){0x000BFFFF, 3, INTC, 0 },
+
+ Package(){0x000CFFFF, 0, INTA, 0 },
+ Package(){0x000CFFFF, 1, INTB, 0 },
+ Package(){0x000CFFFF, 2, INTC, 0 },
+ Package(){0x000CFFFF, 3, INTD, 0 },
+
+ /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+ /* SB devices */
+ /* Bus 0, Dev 17 - SATA controller #2 */
+ /* Bus 0, Dev 18 - SATA controller #1 */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+ * EHCI, dev 18, 19 func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* Package(){0x0014FFFF, 1, INTA, 0 }, */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - RS780 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+ Package(){0x0001FFFF, 0, 0, 18 },
+ Package(){0x0001FFFF, 1, 0, 19 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ /* Package(){0x0002FFFF, 1, 0, 19 }, */
+ /* Package(){0x0002FFFF, 2, 0, 16 }, */
+ /* Package(){0x0002FFFF, 3, 0, 17 }, */
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+ Package(){0x0003FFFF, 0, 0, 19 },
+ Package(){0x0003FFFF, 1, 0, 16 },
+ Package(){0x0003FFFF, 2, 0, 17 },
+ Package(){0x0003FFFF, 3, 0, 18 },
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){0x0005FFFF, 0, 0, 17 },
+ Package(){0x0005FFFF, 1, 0, 18 },
+ Package(){0x0005FFFF, 2, 0, 19 },
+ Package(){0x0005FFFF, 3, 0, 16 },
+
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ Package(){0x0006FFFF, 0, 0, 18 },
+ Package(){0x0006FFFF, 1, 0, 19 },
+ Package(){0x0006FFFF, 2, 0, 16 },
+ Package(){0x0006FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ Package(){0x0007FFFF, 0, 0, 19 },
+ Package(){0x0007FFFF, 1, 0, 16 },
+ Package(){0x0007FFFF, 2, 0, 17 },
+ Package(){0x0007FFFF, 3, 0, 18 },
+
+ /* Bus 0, Dev 9 - PCIe Bridge for network card */
+ Package(){0x0009FFFF, 0, 0, 17 },
+ Package(){0x0009FFFF, 1, 0, 16 },
+ Package(){0x0009FFFF, 2, 0, 17 },
+ Package(){0x0009FFFF, 3, 0, 18 },
+ /* Bus 0, Dev A - PCIe Bridge for network card */
+ Package(){0x000AFFFF, 0, 0, 18 },
+ Package(){0x000AFFFF, 1, 0, 16 },
+ Package(){0x000AFFFF, 2, 0, 17 },
+ Package(){0x000AFFFF, 3, 0, 18 },
+ /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 17 - SATA controller #2 */
+ /* Bus 0, Dev 18 - SATA controller #1 */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+ * EHCI, dev 18, 19 func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+ /* Package(){0x0012FFFF, 2, 0, 18 }, */
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+ /* Package(){0x0013FFFF, 2, 0, 16 }, */
+
+ /* Package(){0x00140000, 0, 0, 16 }, */
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+ /* Package(){0x00140004, 2, 0, 18 }, */
+ /* Package(){0x00140004, 3, 0, 19 }, */
+ /* Package(){0x00140005, 1, 0, 17 }, */
+ /* Package(){0x00140006, 1, 0, 17 }, */
+
+ /* TODO: pcie */
+ Package(){0x0015FFFF, 0, 0, 16 },
+ Package(){0x0015FFFF, 1, 0, 17 },
+ Package(){0x0015FFFF, 2, 0, 18 },
+ Package(){0x0015FFFF, 3, 0, 19 },
+ })
+
+ Name(PR1, Package(){
+ /* Internal graphics - RS780 VGA, Bus1, Dev5 */
+ Package(){0x0005FFFF, 0, INTA, 0 },
+ Package(){0x0005FFFF, 1, INTB, 0 },
+ Package(){0x0005FFFF, 2, INTC, 0 },
+ Package(){0x0005FFFF, 3, INTD, 0 },
+ })
+ Name(APR1, Package(){
+ /* Internal graphics - RS780 VGA, Bus1, Dev5 */
+ Package(){0x0005FFFF, 0, 0, 18 },
+ Package(){0x0005FFFF, 1, 0, 19 },
+ /* Package(){0x0005FFFF, 2, 0, 20 }, */
+ /* Package(){0x0005FFFF, 3, 0, 17 }, */
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PS9, Package(){
+ /* PCIe slot - Hooked to PCIe slot 9 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS9, Package(){
+ /* PCIe slot - Hooked to PCIe slot 9 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PSa, Package(){
+ /* PCIe slot - Hooked to PCIe slot 10 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APSa, Package(){
+ /* PCIe slot - Hooked to PCIe slot 10 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PE0, Package(){
+ /* PCIe slot - Hooked to PCIe slot 10 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APE0, Package(){
+ /* PCIe slot - Hooked to PCIe */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PE1, Package(){
+ /* PCIe slot - Hooked to PCIe slot 10 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APE1, Package(){
+ /* PCIe slot - Hooked to PCIe */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PE2, Package(){
+ /* PCIe slot - Hooked to PCIe slot 10 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APE2, Package(){
+ /* PCIe slot - Hooked to PCIe */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PE3, Package(){
+ /* PCIe slot - Hooked to PCIe slot 10 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APE3, Package(){
+ /* PCIe slot - Hooked to PCIe */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+ Package(){0x0006FFFF, 0, 0, 0x15 },
+ Package(){0x0006FFFF, 1, 0, 0x16 },
+ Package(){0x0006FFFF, 2, 0, 0x17 },
+ Package(){0x0006FFFF, 3, 0, 0x14 },
+ Package(){0x0007FFFF, 0, 0, 0x16 },
+ Package(){0x0007FFFF, 1, 0, 0x17 },
+ Package(){0x0007FFFF, 2, 0, 0x14 },
+ Package(){0x0007FFFF, 3, 0, 0x15 },
+ })
+}
diff --git a/src/mainboard/pcengines/apu1c/acpi/sata.asl b/src/mainboard/pcengines/apu1c/acpi/sata.asl
new file mode 100755
index 0000000..dcf6dec
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/acpi/sata.asl
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(SATA) {
+ Name(_ADR, 0x00110000)
+ #include "sata.asl"
+ }
+ }
+}
+*/
+
+Name(STTM, Buffer(20) {
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+ \_GPE._L1F()
+}
+
+Device(PMRY)
+{
+ Name(_ADR, 0)
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(PMST) {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P0IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ }/* end of PMST */
+
+ Device(PSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P1IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of PSLA */
+} /* end of PMRY */
+
+
+Device(SEDY)
+{
+ Name(_ADR, 1) /* IDE Scondary Channel */
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(SMST)
+ {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P2IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SMST */
+
+ Device(SSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P3IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SSLA */
+} /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+ Method(_L1F,0x0,NotSerialized) {
+ if (\_SB.P0PR) {
+ if (LGreater(\_SB.P0IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P0PR)
+ }
+
+ if (\_SB.P1PR) {
+ if (LGreater(\_SB.P1IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P1PR)
+ }
+
+ if (\_SB.P2PR) {
+ if (LGreater(\_SB.P2IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P2PR)
+ }
+
+ if (\_SB.P3PR) {
+ if (LGreater(\_SB.P3IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P3PR)
+ }
+ }
+}
diff --git a/src/mainboard/pcengines/apu1c/acpi/sleep.asl b/src/mainboard/pcengines/apu1c/acpi/sleep.asl
new file mode 100644
index 0000000..5d0f8f0
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/acpi/sleep.asl
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ if (LEqual(Arg0,3)){
+ Store(0,URRE)
+ }
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ if (LEqual(Arg0,3)){
+ Store(1,URRE)
+ }
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ Store(PWST, PWST)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/pcengines/apu1c/acpi/smbus.asl b/src/mainboard/pcengines/apu1c/acpi/smbus.asl
new file mode 100644
index 0000000..b2e01b7
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/acpi/smbus.asl
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* SMBUS Support */
+Mutex (SBX0, 0x00)
+OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+ Field (SMB0, ByteAcc, NoLock, Preserve) {
+ HSTS, 8, /* SMBUS status */
+ SSTS, 8, /* SMBUS slave status */
+ HCNT, 8, /* SMBUS control */
+ HCMD, 8, /* SMBUS host cmd */
+ HADD, 8, /* SMBUS address */
+ DAT0, 8, /* SMBUS data0 */
+ DAT1, 8, /* SMBUS data1 */
+ BLKD, 8, /* SMBUS block data */
+ SCNT, 8, /* SMBUS slave control */
+ SCMD, 8, /* SMBUS shadow cmd */
+ SEVT, 8, /* SMBUS slave event */
+ SDAT, 8 /* SMBUS slave data */
+}
+
+Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+ Store (0x1E, HSTS)
+ Store (0xFA, Local0)
+ While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+ Stall (0x64)
+ Decrement (Local0)
+ }
+
+ Return (Local0)
+}
+
+Method (SWTC, 1, NotSerialized) {
+ Store (Arg0, Local0)
+ Store (0x07, Local2)
+ Store (One, Local1)
+ While (LEqual (Local1, One)) {
+ Store (And (HSTS, 0x1E), Local3)
+ If (LNotEqual (Local3, Zero)) { /* read sucess */
+ If (LEqual (Local3, 0x02)) {
+ Store (Zero, Local2)
+ }
+
+ Store (Zero, Local1)
+ }
+ Else {
+ If (LLess (Local0, 0x0A)) { /* read failure */
+ Store (0x10, Local2)
+ Store (Zero, Local1)
+ }
+ Else {
+ Sleep (0x0A) /* 10 ms, try again */
+ Subtract (Local0, 0x0A, Local0)
+ }
+ }
+ }
+
+ Return (Local2)
+}
+
+Method (SMBR, 3, NotSerialized) {
+ Store (0x07, Local0)
+ If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+ Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+ If (LEqual (Local0, Zero)) {
+ Release (SBX0)
+ Return (0x0)
+ }
+
+ Store (0x1F, HSTS)
+ Store (Or (ShiftLeft (Arg1, One), One), HADD)
+ Store (Arg2, HCMD)
+ If (LEqual (Arg0, 0x07)) {
+ Store (0x48, HCNT) /* read byte */
+ }
+
+ Store (SWTC (0x03E8), Local1) /* 1000 ms */
+ If (LEqual (Local1, Zero)) {
+ If (LEqual (Arg0, 0x07)) {
+ Store (DAT0, Local0)
+ }
+ }
+ Else {
+ Store (Local1, Local0)
+ }
+
+ Release (SBX0)
+ }
+
+ /* DBGO("the value of SMBusData0 register ") */
+ /* DBGO(Arg2) */
+ /* DBGO(" is ") */
+ /* DBGO(Local0) */
+ /* DBGO("\n") */
+
+ Return (Local0)
+}
diff --git a/src/mainboard/pcengines/apu1c/acpi/superio.asl b/src/mainboard/pcengines/apu1c/acpi/superio.asl
new file mode 100644
index 0000000..7d8d9df
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/acpi/superio.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* No SuperIO device or functionality yet */
diff --git a/src/mainboard/pcengines/apu1c/acpi/thermal.asl b/src/mainboard/pcengines/apu1c/acpi/thermal.asl
new file mode 100644
index 0000000..2f50475
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/acpi/thermal.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Thermal Zones have been #if 0 for a long time.
+ * Removing it for now because it doesn't seem to
+ * do anything when enabled anyway.
+ */
diff --git a/src/mainboard/pcengines/apu1c/acpi/usb_oc.asl b/src/mainboard/pcengines/apu1c/acpi/usb_oc.asl
new file mode 100644
index 0000000..d79d64e
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/acpi/usb_oc.asl
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
+
+Method(UCOC, 0) {
+ Sleep(20)
+ Store(0x13,CMTI)
+ Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+ Scope (\_GPE) {
+ Method (_L13) {
+ UCOC()
+ if(LEqual(GPB0,PLC0)) {
+ Not(PLC0,PLC0)
+ Store(PLC0, \_SB.PT0D)
+ }
+ }
+ }
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+ Scope (\_GPE) {
+ Method (_L14) {
+ UCOC()
+ if (LEqual(GPB1,PLC1)) {
+ Not(PLC1,PLC1)
+ Store(PLC1, \_SB.PT1D)
+ }
+ }
+ }
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+ Scope (\_GPE) {
+ Method (_L15) {
+ UCOC()
+ if (LEqual(GPB2,PLC2)) {
+ Not(PLC2,PLC2)
+ Store(PLC2, \_SB.PT2D)
+ }
+ }
+ }
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+ Scope (\_GPE) {
+ Method (_L16) {
+ UCOC()
+ if (LEqual(GPB3,PLC3)) {
+ Not(PLC3,PLC3)
+ Store(PLC3, \_SB.PT3D)
+ }
+ }
+ }
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+ Scope (\_GPE) {
+ Method (_L19) {
+ UCOC()
+ if (LEqual(GPB4,PLC4)) {
+ Not(PLC4,PLC4)
+ Store(PLC4, \_SB.PT4D)
+ }
+ }
+ }
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+ Scope (\_GPE) {
+ Method (_L1A) {
+ UCOC()
+ if (LEqual(GPB5,PLC5)) {
+ Not(PLC5,PLC5)
+ Store(PLC5, \_SB.PT5D)
+ }
+ }
+ }
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1C) { */
+ Method (_L06) {
+ UCOC()
+ if (LEqual(GPB6,PLC6)) {
+ Not(PLC6,PLC6)
+ Store(PLC6, \_SB.PT6D)
+ }
+ }
+ }
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1D) { */
+ Method (_L07) {
+ UCOC()
+ if (LEqual(GPB7,PLC7)) {
+ Not(PLC7,PLC7)
+ Store(PLC7, \_SB.PT7D)
+ }
+ }
+ }
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+ Scope (\_GPE) {
+ Method (_L17) {
+ if (LEqual(G8IS,PLC8)) {
+ Not(PLC8,PLC8)
+ Store(PLC8, \_SB.PT8D)
+ }
+ }
+ }
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+ Scope (\_GPE) {
+ Method (_L0E) {
+ if (LEqual(G9IS,0)) {
+ Store(1,\_SB.PT9D)
+ }
+ }
+ }
+}
diff --git a/src/mainboard/pcengines/apu1c/acpi_tables.c b/src/mainboard/pcengines/apu1c/acpi_tables.c
new file mode 100755
index 0000000..65cb796
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/acpi_tables.c
@@ -0,0 +1,267 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <console/console.h>
+#include <cpu/amd/amdfam14.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+
+extern const unsigned char AmlCode[];
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+ int lens;
+ msr_t msr;
+ char pscope[] = "\\_SB.PCI0";
+
+ lens = acpigen_write_scope(pscope);
+ msr = rdmsr(TOP_MEM);
+ lens += acpigen_write_name_dword("TOM1", msr.lo);
+ msr = rdmsr(TOP_MEM2);
+ /*
+ * Since XP only implements parts of ACPI 2.0, we can't use a qword
+ * here.
+ * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+ * slide 22ff.
+ * Shift value right by 20 bit to make it fit into 32bit,
+ * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+ */
+ lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+ acpigen_patch_len(lens - 1);
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /* Just a dummy */
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB800 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
+
+unsigned long acpi_fill_hest(acpi_hest_t *hest)
+{
+ void *addr, *current;
+
+ /* Skip the HEST header. */
+ current = (void *)(hest + 1);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ return (unsigned long)current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_srat_t *srat;
+ acpi_slit_t *slit;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ acpi_header_t *ssdt;
+ acpi_header_t *ssdt2;
+ acpi_header_t *alib;
+ acpi_hest_t *hest;
+
+ /* Align ACPI tables to 16 bytes */
+ start = ALIGN(start, 16);
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /* DSDT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
+ dsdt = (acpi_header_t *)current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+ /* FACS */ // it needs 64 bit alignment
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* FADT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+
+ /* HEST */
+ current = ALIGN(current, 8);
+ hest = (acpi_hest_t *)current;
+ acpi_write_hest((void *)current);
+ acpi_add_table(rsdp, (void *)current);
+ current += ((acpi_header_t *)current)->length;
+
+ /* SRAT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
+ srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+ if (srat != NULL) {
+ memcpy((void *)current, srat, srat->header.length);
+ srat = (acpi_srat_t *) current;
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
+ }
+
+ /* SLIT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
+ slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+ if (slit != NULL) {
+ memcpy((void *)current, slit, slit->header.length);
+ slit = (acpi_slit_t *) current;
+ current += slit->header.length;
+ acpi_add_table(rsdp, slit);
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
+ }
+
+ /* SSDT */
+ current = ALIGN(current, 16);
+ printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
+ alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+ if (alib != NULL) {
+ memcpy((void *)current, alib, alib->length);
+ alib = (acpi_header_t *) current;
+ current += alib->length;
+ acpi_add_table(rsdp, (void *)alib);
+ } else {
+ printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
+ }
+
+ /* The DSDT needs additional work for the AGESA SSDT Pstate table */
+ /* Keep the comment for a while. */
+ current = ALIGN(current, 16);
+ printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current);
+ ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+ if (ssdt != NULL) {
+ memcpy((void *)current, ssdt, ssdt->length);
+ ssdt = (acpi_header_t *) current;
+ current += ssdt->length;
+ acpi_add_table(rsdp,ssdt);
+ } else {
+ printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n");
+ }
+
+ current = ALIGN(current, 16);
+ printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current);
+ ssdt2 = (acpi_header_t *) current;
+ acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
+ current += ssdt2->length;
+ acpi_add_table(rsdp,ssdt2);
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/pcengines/apu1c/agesawrapper.c b/src/mainboard/pcengines/apu1c/agesawrapper.c
new file mode 100755
index 0000000..2521197
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/agesawrapper.c
@@ -0,0 +1,628 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include "PlatformGnbPcieComplex.h"
+
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <cpu/amd/agesa/s3_resume.h>
+#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+#define MMCONF_ENABLE 1
+
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable = NULL;
+VOID *AcpiPstate = NULL;
+VOID *AcpiSrat = NULL;
+VOID *AcpiSlit = NULL;
+
+VOID *AcpiWheaMce = NULL;
+VOID *AcpiWheaCmc = NULL;
+VOID *AcpiAlib = NULL;
+
+/*------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *------------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *------------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *------------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *------------------------------------------------------------------------------
+ */
+AGESA_STATUS agesawrapper_amdinitcpuio (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+#if 0
+ /* Enable legacy video routing: D18F1xF4 VGA Enable */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+ PciData = 1;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+#endif
+
+ /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+ * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+ * set to non-posted regions.
+ */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+ PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
+ PciData |= 1 << 7; // set NP (non-posted) bit
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+ PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Map the remaining PCI hole as posted MMIO */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+ PciData = 0x00FECF00; // last address before non-posted range
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ MsrReg = (MsrReg >> 8) | 3;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+ PciData = (UINT32)MsrReg;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Send all IO (0000-FFFF) to southbridge. */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+ PciData = 0x0000F000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+ PciData = 0x00000003;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ Status = AGESA_SUCCESS;
+ return Status;
+}
+
+AGESA_STATUS agesawrapper_amdinitmmio (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ UINT8 BusRangeVal = 0;
+ UINT8 BusNum;
+ UINT8 Index;
+
+ /*
+ Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+ Address MSR register.
+ */
+
+ for (Index = 0; Index < 8; Index++) {
+ BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
+ if (BusNum == 1) {
+ BusRangeVal = Index;
+ break;
+ }
+ }
+
+ MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
+ LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+ /*
+ Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+ */
+ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+ MsrReg = MsrReg | 0x0000400000000000ull;
+ LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+ /* Set Ontario Link Data */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
+ PciData = 0x01308002;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
+ PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ Status = AGESA_SUCCESS;
+ return Status;
+}
+
+AGESA_STATUS agesawrapper_amdinitreset (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESET_PARAMS AmdResetParams;
+
+ memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
+ memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+ AmdParamStruct.AllocationMethod = ByHost;
+ AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+ AmdParamStruct.NewStructPtr = &AmdResetParams;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = NULL;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+ AmdResetParams.HtConfig.Depth = 0;
+
+ status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+ AmdReleaseStruct (&AmdParamStruct);
+ return status;
+}
+
+AGESA_STATUS agesawrapper_amdinitearly (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
+
+ memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+
+ AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+ OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+ status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return status;
+}
+
+AGESA_STATUS agesawrapper_amdinitpost (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+ status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+ AmdReleaseStruct (&AmdParamStruct);
+
+ /* Initialize heap space */
+ EmptyHeap();
+
+ return status;
+}
+
+AGESA_STATUS agesawrapper_amdinitenv (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ PCI_ADDR PciAddress;
+ UINT32 PciValue;
+
+ memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+ status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+ /* Initialize Subordinate Bus Number and Secondary Bus Number
+ * In platform BIOS this address is allocated by PCI enumeration code
+ Modify D1F0x18
+ */
+ PciAddress.Address.Bus = 0;
+ PciAddress.Address.Device = 1;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x18;
+ /* Write to D1F0x18 */
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x00010100;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize GMM Base Address for Legacy Bridge Mode
+ * Modify B1D5F0x18
+ */
+ PciAddress.Address.Bus = 1;
+ PciAddress.Address.Device = 5;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x18;
+
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x96000000;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize FB Base Address for Legacy Bridge Mode
+ * Modify B1D5F0x10
+ */
+ PciAddress.Address.Register = 0x10;
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x80000000;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize GMM Base Address for Pcie Mode
+ * Modify B0D1F0x18
+ */
+ PciAddress.Address.Bus = 0;
+ PciAddress.Address.Device = 1;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x18;
+
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x96000000;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize FB Base Address for Pcie Mode
+ * Modify B0D1F0x10
+ */
+ PciAddress.Address.Register = 0x10;
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x80000000;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize MMIO Base and Limit Address
+ * Modify B0D1F0x20
+ */
+ PciAddress.Address.Bus = 0;
+ PciAddress.Address.Device = 1;
+ PciAddress.Address.Function = 0;
+ PciAddress.Address.Register = 0x20;
+
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x96009600;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+ /* Initialize MMIO Prefetchable Memory Limit and Base
+ * Modify B0D1F0x24
+ */
+ PciAddress.Address.Register = 0x24;
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ PciValue |= 0x8FF18001;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return status;
+}
+
+VOID *
+agesawrapper_getlateinitptr (
+ int pick
+ )
+{
+ switch (pick) {
+ case PICK_DMI:
+ return DmiTable;
+ case PICK_PSTATE:
+ return AcpiPstate;
+ case PICK_SRAT:
+ return AcpiSrat;
+ case PICK_SLIT:
+ return AcpiSlit;
+ case PICK_WHEA_MCE:
+ return AcpiWheaMce;
+ case PICK_WHEA_CMC:
+ return AcpiWheaCmc;
+ case PICK_ALIB:
+ return AcpiAlib;
+ default:
+ return NULL;
+ }
+}
+
+AGESA_STATUS agesawrapper_amdinitmid (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ /* Enable MMIO on AMD CPU Address Map Controller */
+ agesawrapper_amdinitcpuio ();
+
+ memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+
+ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return status;
+}
+
+AGESA_STATUS agesawrapper_amdinitlate (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_LATE_PARAMS * AmdLateParamsPtr;
+
+ memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+ AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
+
+ printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
+
+ Status = AmdInitLate (AmdLateParamsPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog();
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ DmiTable = AmdLateParamsPtr->DmiTable;
+ AcpiPstate = AmdLateParamsPtr->AcpiPState;
+ AcpiSrat = AmdLateParamsPtr->AcpiSrat;
+ AcpiSlit = AmdLateParamsPtr->AcpiSlit;
+ AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
+ AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
+ AcpiAlib = AmdLateParamsPtr->AcpiAlib;
+
+ printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
+ " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
+ " Mce:%p\n Cmc:%p\n Alib:%p\n",
+ __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
+ AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
+
+ /* Don't release the structure until coreboot has copied the ACPI tables.
+ * AmdReleaseStruct (&AmdLateParams);
+ */
+
+ return Status;
+}
+
+AGESA_STATUS agesawrapper_amdinitresume (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESUME_PARAMS *AmdResumeParamsPtr;
+ S3_DATA_TYPE S3DataType;
+
+ memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+
+ AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
+
+ AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
+ AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
+ S3DataType = S3DataTypeNonVolatile;
+
+ OemAgesaGetS3Info (S3DataType,
+ (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
+ (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
+
+ status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
+
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return status;
+}
+
+AGESA_STATUS agesawrapper_amds3laterestore (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ AMD_INTERFACE_PARAMS AmdInterfaceParams;
+ AMD_S3LATE_PARAMS AmdS3LateParams;
+ AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
+ S3_DATA_TYPE S3DataType;
+
+ memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS));
+
+ AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
+ AmdInterfaceParams.AllocationMethod = ByHost;
+ AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
+ AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
+ AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdS3LateParamsPtr = &AmdS3LateParams;
+ AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
+
+ AmdCreateStruct (&AmdInterfaceParams);
+
+ AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
+ S3DataType = S3DataTypeVolatile;
+
+ OemAgesaGetS3Info (S3DataType,
+ (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
+ (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
+
+ Status = AmdS3LateRestore (AmdS3LateParamsPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog();
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ return Status;
+}
+
+#ifndef __PRE_RAM__
+AGESA_STATUS agesawrapper_amdS3Save (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
+ AMD_INTERFACE_PARAMS AmdInterfaceParams;
+ S3_DATA_TYPE S3DataType;
+
+ memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS));
+
+ AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
+ AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdInterfaceParams.AllocationMethod = PostMemDram;
+ AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
+ AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
+ AmdInterfaceParams.StdHeader.Func = 0;
+ AmdCreateStruct(&AmdInterfaceParams);
+
+ AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
+ AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
+
+ Status = AmdS3Save (AmdS3SaveParamsPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog();
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ S3DataType = S3DataTypeNonVolatile;
+
+ Status = OemAgesaSaveS3Info (
+ S3DataType,
+ AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
+ AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
+
+ if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
+ S3DataType = S3DataTypeVolatile;
+
+ Status = OemAgesaSaveS3Info (
+ S3DataType,
+ AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
+ AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage
+ );
+ }
+
+ OemAgesaSaveMtrr();
+ AmdReleaseStruct (&AmdInterfaceParams);
+
+ return Status;
+}
+#endif /* #ifndef __PRE_RAM__ */
+
+AGESA_STATUS agesawrapper_amdlaterunaptask (
+ UINT32 Func,
+ UINT32 Data,
+ VOID *ConfigPtr
+ )
+{
+ AGESA_STATUS Status;
+ AP_EXE_PARAMS ApExeParams;
+
+ memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
+
+ ApExeParams.StdHeader.AltImageBasePtr = 0;
+ ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ ApExeParams.StdHeader.Func = 0;
+ ApExeParams.StdHeader.ImageBasePtr = 0;
+ ApExeParams.FunctionNumber = Func;
+ ApExeParams.RelatedDataBlock = ConfigPtr;
+
+ Status = AmdLateRunApTask (&ApExeParams);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog();
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ return Status;
+}
+
+AGESA_STATUS agesawrapper_amdreadeventlog (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ EVENT_PARAMS AmdEventParams;
+
+ memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS));
+
+ AmdEventParams.StdHeader.AltImageBasePtr = 0;
+ AmdEventParams.StdHeader.CalloutPtr = NULL;
+ AmdEventParams.StdHeader.Func = 0;
+ AmdEventParams.StdHeader.ImageBasePtr = 0;
+ Status = AmdReadEventLog (&AmdEventParams);
+ while (AmdEventParams.EventClass != 0) {
+ printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+ printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+ printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+ Status = AmdReadEventLog (&AmdEventParams);
+ }
+
+ return Status;
+}
diff --git a/src/mainboard/pcengines/apu1c/agesawrapper.h b/src/mainboard/pcengines/apu1c/agesawrapper.h
new file mode 100755
index 0000000..b8c3f6c
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/agesawrapper.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AGESAWRAPPER_H_
+#define _AGESAWRAPPER_H_
+
+#include <stdint.h>
+#include "Porting.h"
+#include "AGESA.h"
+
+/* Define AMD Ontario APPU SSID/SVID */
+#define AMD_APU_SVID 0x1022
+#define AMD_APU_SSID 0x1234
+#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+
+enum {
+ PICK_DMI, /* DMI Interface */
+ PICK_PSTATE, /* Acpi Pstate SSDT Table */
+ PICK_SRAT, /* SRAT Table */
+ PICK_SLIT, /* SLIT Table */
+ PICK_WHEA_MCE, /* WHEA MCE table */
+ PICK_WHEA_CMC, /* WHEA CMV table */
+ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
+};
+
+AGESA_STATUS agesawrapper_amdinitreset(void);
+AGESA_STATUS agesawrapper_amdinitearly(void);
+AGESA_STATUS agesawrapper_amdinitenv(void);
+AGESA_STATUS agesawrapper_amdinitlate(void);
+AGESA_STATUS agesawrapper_amdinitpost(void);
+AGESA_STATUS agesawrapper_amdinitmid(void);
+
+AGESA_STATUS agesawrapper_amdreadeventlog(void);
+
+AGESA_STATUS agesawrapper_amdinitcpuio(void);
+AGESA_STATUS agesawrapper_amdinitmmio(void);
+AGESA_STATUS agesawrapper_amdinitresume(void);
+AGESA_STATUS agesawrapper_amdS3Save(void);
+AGESA_STATUS agesawrapper_amds3laterestore(void);
+AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+void *agesawrapper_getlateinitptr (int pick);
+
+#endif
diff --git a/src/mainboard/pcengines/apu1c/board_info.txt b/src/mainboard/pcengines/apu1c/board_info.txt
new file mode 100644
index 0000000..120c8fd
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/board_info.txt
@@ -0,0 +1,6 @@
+Category: sbc
+Board URL: http://www.pcengines.ch/apu1c.htm
+ROM package: SOP8
+ROM protocol: [http://www.macronix.com/Lists/DataSheet/Attachments/1545/MX25L1605,%203V,%2016Mb,%20v1.3.pdf MX25L1605 SPI]
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/pcengines/apu1c/buildOpts.c b/src/mainboard/pcengines/apu1c/buildOpts.c
new file mode 100755
index 0000000..b36de4b
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/buildOpts.c
@@ -0,0 +1,476 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
+ */
+
+#include <stdlib.h>
+
+#include "Filecode.h"
+#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
+
+
+/* Select the cpu family. */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT FALSE
+#define INSTALL_FAMILY_14_SUPPORT TRUE
+#define INSTALL_FAMILY_15_SUPPORT FALSE
+
+/* Select the cpu socket type. */
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP1_SOCKET_SUPPORT FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT TRUE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
+#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE
+#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE
+#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
+
+#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE
+#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
+
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT FALSE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE
+#define BLDOPT_REMOVE_DQS_TRAINING FALSE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+ #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
+ #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
+ #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
+ #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
+ #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
+ #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
+#define BLDOPT_REMOVE_SRAT FALSE
+#define BLDOPT_REMOVE_SLIT FALSE
+#define BLDOPT_REMOVE_WHEA FALSE
+#define BLDOPT_REMOVE_DMI TRUE
+#define BLDOPT_REMOVE_HT_ASSIST TRUE
+#define BLDOPT_REMOVE_ATM_MODE TRUE
+//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
+//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
+#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
+//#define BLDOPT_REMOVE_C6_STATE TRUE
+#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
+#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
+
+/*
+ * Agesa entry points used in this implementation.
+ */
+#define AGESA_ENTRY_INIT_RESET TRUE
+#define AGESA_ENTRY_INIT_RECOVERY FALSE
+#define AGESA_ENTRY_INIT_EARLY TRUE
+#define AGESA_ENTRY_INIT_POST TRUE
+#define AGESA_ENTRY_INIT_ENV TRUE
+#define AGESA_ENTRY_INIT_MID TRUE
+#define AGESA_ENTRY_INIT_LATE TRUE
+#define AGESA_ENTRY_INIT_S3SAVE TRUE
+#define AGESA_ENTRY_INIT_RESUME TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+
+#define BLDCFG_VRM_CURRENT_LIMIT 24000
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1
+#define BLDCFG_VRM_SLEW_RATE 5000
+//#define BLDCFG_VRM_NB_SLEW_RATE 5000
+//#define BLDCFG_VRM_ADDITIONAL_DELAY 0
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
+#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0
+
+//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
+//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled
+//#define BLDCFG_PLATFORM_C1E_OPDATA 0
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
+#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
+//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+//#define BLDCFG_STARTING_BUSNUM 0
+//#define BLDCFG_MAXIMUM_BUSNUM 0xf8
+//#define BLDCFG_ALLOCATED_BUSNUMS 0x20
+//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0
+//#define BLDCFG_BUID_SWAP_LIST 0
+//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0
+//#define BLDCFG_HTFABRIC_LIMITS_LIST 0
+//#define BLDCFG_HTCHAIN_LIMITS_LIST 0
+//#define BLDCFG_BUS_NUMBERS_LIST 0
+//#define BLDCFG_IGNORE_LINK_LIST 0
+//#define BLDCFG_LINK_SKIP_REGANG_LIST 0
+//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0
+//#define BLDCFG_USE_HT_ASSIST TRUE
+//#define BLDCFG_USE_ATM_MODE TRUE
+//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
+#define BLDCFG_S3_LATE_RESTORE TRUE
+//#define BLDCFG_USE_32_BYTE_REFRESH FALSE
+//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
+//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance
+//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
+//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
+//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
+#define BLDCFG_CFG_GNB_HD_AUDIO FALSE
+//#define BLDCFG_CFG_ABM_SUPPORT FALSE
+//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
+//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0
+//#define BLDCFG_MEM_INIT_PSTATE 0
+//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+//#define BLDCFG_ONLINE_SPARE FALSE
+//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+//#define BLDCFG_ENABLE_ECC_FEATURE TRUE
+//#define BLDCFG_ECC_REDIRECTION FALSE
+//#define BLDCFG_SCRUB_DRAM_RATE 0
+//#define BLDCFG_SCRUB_L2_RATE 0
+//#define BLDCFG_SCRUB_L3_RATE 0
+//#define BLDCFG_SCRUB_IC_RATE 0
+//#define BLDCFG_SCRUB_DC_RATE 0
+//#define BLDCFG_ECC_SYNC_FLOOD 0
+//#define BLDCFG_ECC_SYMBOL_SIZE 0
+//#define BLDCFG_1GB_ALIGN FALSE
+#if !CONFIG_GFXUMA
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE
+#else
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
+#endif
+#define BLDCFG_UMA_ALLOCATION_SIZE 0
+#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
+#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
+
+/*
+ * Agesa configuration values selection.
+ * Uncomment and specify the value for the configuration options
+ * needed by the system.
+ */
+#include "AGESA.h"
+#include "CommonReturns.h"
+
+/* The fixed MTRR values to be set after memory initialization. */
+CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
+ { CPU_LIST_TERMINAL }
+};
+
+/* Include the files that instantiate the configuration definitions. */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+/*****************************************************************************
+ * Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+// This is the delivery package title, "BrazosPI"
+// This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+// This is the release version number of the AGESA component
+// This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ //
+ // The following macros are supported (use comma to separate macros):
+ //
+ // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+ // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+ // AGESA will base on this value to disable unused MemClk to save power.
+ // Example:
+ // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+ // Bit AM3/S1g3 pin name
+ // 0 M[B,A]_CLK_H/L[0]
+ // 1 M[B,A]_CLK_H/L[1]
+ // 2 M[B,A]_CLK_H/L[2]
+ // 3 M[B,A]_CLK_H/L[3]
+ // 4 M[B,A]_CLK_H/L[4]
+ // 5 M[B,A]_CLK_H/L[5]
+ // 6 M[B,A]_CLK_H/L[6]
+ // 7 M[B,A]_CLK_H/L[7]
+ // And platform has the following routing:
+ // CS0 M[B,A]_CLK_H/L[4]
+ // CS1 M[B,A]_CLK_H/L[2]
+ // CS2 M[B,A]_CLK_H/L[3]
+ // CS3 M[B,A]_CLK_H/L[5]
+ // Then platform can specify the following macro:
+ // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+ //
+ // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+ // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+ // AGESA will base on this value to tristate unused CKE to save power.
+ //
+ // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+ // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+ // AGESA will base on this value to tristate unused ODT pins to save power.
+ //
+ // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+ // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+ // AGESA will base on this value to tristate unused Chip select to save power.
+ //
+ // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+ // Specifies the number of DIMM slots per channel.
+ //
+ // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+ // Specifies the number of Chip selects per channel.
+ //
+ // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+ // Specifies the number of channels per socket.
+ //
+ // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+ // Specifies DDR bus speed of channel ChannelID on socket SocketID.
+ //
+ // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+ // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+ //
+ // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ // Byte6Seed, Byte7Seed, ByteEccSeed)
+ // Specifies the write leveling seed for a channel of a socket.
+ //
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
+
+ // APU1C soldered down memory uses memory CLK0/CS0
+ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+
+ // APU1C soldered down memory requires different seeds due to shorter trace length.
+ // http://subscriptions.amd.com/assets/pdf/zen_memory_whitepaper_final.pdf
+ // The values below are copied from the similar gizmo board.
+#define WLSEED 0x08
+#define RXSEED 0x40
+ WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
+ HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
+
+ PSO_END
+};
+
+/*
+ * These tables are optional and may be used to adjust memory timing settings
+ */
+#include "mm.h"
+#include "mn.h"
+
+//DA Customer table
+CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
+{
+ // Hardcoded Memory Training Values
+
+ // The following macro should be used to override training values for your platform
+ //
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+ //
+ // NOTE:
+ // The following training hardcode values are example values that were taken from a tilapia motherboard
+ // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
+ // the table and replace the byte lane values with your own.
+ //
+ // ------------------ BYTE LANES ----------------------
+ // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
+ // Write Data Timing
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+ // DQS Receiver Enable
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+ // Write DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+ // Read DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+ //--------------------------------------------------------------------------------------------------------------------------------------------------
+ // TABLE END
+ NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
+};
+CONST UINT8 SizeOfTableON = ARRAY_SIZE(AGESA_MEM_TABLE_ON);
+
+/* ***************************************************************************
+ * Optional User code to be included into the AGESA build
+ * These may be 32-bit call-out routines...
+ */
+//AGESA_STATUS
+//AgesaReadSpd (
+// IN UINTN FcnData,
+// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
+// )
+//{
+// /* platform code to read an SPD... */
+// return Status;
+//}
diff --git a/src/mainboard/pcengines/apu1c/cmos.layout b/src/mainboard/pcengines/apu1c/cmos.layout
new file mode 100755
index 0000000..ab65be0
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/cmos.layout
@@ -0,0 +1,116 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#*****************************************************************************
+
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/pcengines/apu1c/devicetree.cb b/src/mainboard/pcengines/apu1c/devicetree.cb
new file mode 100755
index 0000000..d698308
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/devicetree.cb
@@ -0,0 +1,81 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+chip northbridge/amd/agesa/family14/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family14
+ device lapic 0 on end
+ end
+ end
+ device domain 0 on
+ subsystemid 0x1022 0x1510 inherit
+ chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+ chip northbridge/amd/agesa/family14 # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
+ device pci 4.0 on end # PCIE P2P bridge 0x9604
+ device pci 5.0 on end # PCIE P2P bridge 0x9605
+ device pci 6.0 on end # PCIE P2P bridge 0x9606
+ device pci 7.0 off end # PCIE P2P bridge 0x9607
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ end # agesa northbridge
+
+ chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on end # SM
+ device pci 14.1 off end # IDE 0x439c
+ device pci 14.2 off end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/nuvoton/nct5104d
+ device pnp 2e.0 off end # Fdc
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.10 off end # Com3
+ device pnp 2e.11 off end # Com4
+ end #superio/nuvoton/nct5104d
+ end
+ device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed
+ device pci 14.5 off end # USB 2
+ device pci 15.0 on end # PCIe PortA # PCIe x1 to high speed edge connector
+ device pci 15.1 off end # PCIe PortB # PCIe x1 to high speed edge connector
+ device pci 16.0 on end # OHCI USB3
+ device pci 16.2 on end # EHCI USB3
+ register "gpp_configuration" = "4" # GPP_CFGMODE_X1111
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ end #southbridge/amd/cimx/sb800
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+ device pci 18.6 on end
+ device pci 18.7 on end
+ end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+ end #domain
+end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/pcengines/apu1c/dsdt.asl b/src/mainboard/pcengines/apu1c/dsdt.asl
new file mode 100755
index 0000000..727be38
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/dsdt.asl
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "PCENG ", /* OEMID */
+ "COREBOOT", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ #include "acpi/mainboard.asl"
+
+ #include <cpu/amd/agesa/family14/acpi/cpu.asl>
+
+ #include "acpi/routing.asl"
+
+ Scope(\_SB) {
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ Device(PCI0) {
+
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/cimx/sb800/acpi/fch.asl>
+
+ }
+ } /* End Scope(_SB) */
+
+ /* Contains the supported sleep states for this chipset */
+ #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
+
+ /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
+ #include "acpi/sleep.asl"
+
+ #include "acpi/gpe.asl"
+ #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
+ #include "acpi/thermal.asl"
+}
+/* End of ASL file */
diff --git a/src/mainboard/pcengines/apu1c/irq_tables.c b/src/mainboard/pcengines/apu1c/irq_tables.c
new file mode 100755
index 0000000..bb33568
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/irq_tables.c
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam14.h>
+
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+
+
+ slot_num++;
+
+
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+
+}
diff --git a/src/mainboard/pcengines/apu1c/mainboard.c b/src/mainboard/pcengines/apu1c/mainboard.c
new file mode 100755
index 0000000..a98a179
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/mainboard.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/cimx/cimx_util.h>
+
+//#define SMBUS_IO_BASE 0x6000
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * TODO
+ * mainboard specific SB CIMx callback
+ */
+void set_pcie_dereset(void)
+{
+}
+
+
+/**********************************************
+ * Enable the dedicated functions of the board.
+ **********************************************/
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ /*
+ * Initialize ASF registers to an arbitrary address because someone
+ * long ago set things up this way inside the SPD read code. The
+ * SPD read code has been made generic and moved out of the board
+ * directory, so the ASF init is being done here.
+ */
+ pm_iowrite(0x29, 0x80);
+ pm_iowrite(0x28, 0x61);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/pcengines/apu1c/mptable.c b/src/mainboard/pcengines/apu1c/mptable.c
new file mode 100755
index 0000000..9de9e75
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/mptable.c
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
+#include <console/console.h>
+#include <cpu/amd/amdfam14.h>
+#include <device/pci.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
+
+
+u8 intr_data[] = {
+ [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "PCENG ", 8);
+
+ smp_write_processors(mc);
+
+ mptable_write_buses(mc, NULL, &bus_isa);
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+
+ u8 byte;
+
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, fn, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
+
+ /* APU Internal Graphic Device*/
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+ /* Southbridge HD Audio: */
+ PCI_INT(0x0, 0x14, 0x2, 0x12);
+
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
+
+ /* PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/pcengines/apu1c/platform_cfg.h b/src/mainboard/pcengines/apu1c/platform_cfg.h
new file mode 100755
index 0000000..e7a4fc9
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/platform_cfg.h
@@ -0,0 +1,233 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _PLATFORM_CFG_H_
+#define _PLATFORM_CFG_H_
+
+/**
+ * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M
+ *
+ * In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#ifndef BIOS_SIZE
+#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
+#endif /* BIOS_SIZE */
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ * 0 - Disable Spread Spectrum function
+ * 1 - Enable Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @brief
+ * 0 - Disable hpet
+ * 1 - Enable hpet
+ */
+#define HPET_TIMER 1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ * 0 - Disable
+ * 1 - Enable
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG 0x3F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @brief bit[0-4] used for PCI Slots Clock Control,
+ * 0 - disable
+ * 1 - enable
+ * PCI SLOT 0 define at BIT0
+ * PCI SLOT 1 define at BIT1
+ * PCI SLOT 2 define at BIT2
+ * PCI SLOT 3 define at BIT3
+ * PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL 0x02 /* Enable only LPC clock */
+
+/**
+ * @def SATA_CONTROLLER
+ * @brief INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @brief INCHIP Sata Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE CONFIG_SB800_SATA_MODE
+
+/**
+ * @brief INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE 0
+#define IDE_NATIVE_MODE 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @brief INCHIP Sata IDE Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ * PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK 0x00
+#define INTERNAL_CLOCK 0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+
+/**
+ * @def AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @brief INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER AZALIA_DISABLE
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ * 0 - disable
+ * 1 - enable
+ */
+#define AZALIA_PIN_CONFIG 0
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ * SDIN0 is define at BIT0 & BIT1
+ * 00 - GPIO PIN
+ * 01 - Reserved
+ * 10 - As a Azalia SDIN pin
+ * SDIN1 is define at BIT2 & BIT3
+ * SDIN2 is define at BIT4 & BIT5
+ * SDIN3 is define at BIT6 & BIT7
+ */
+#define AZALIA_SDIN_PIN 0xAA
+
+/**
+ * @def AZALIA_OEM_VERB_TABLE
+ * Mainboard specific codec verb table list
+ */
+// #define AZALIA_OEM_VERB_TABLE // No codec present.
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ * GPP_CFGMODE_X4000
+ * GPP_CFGMODE_X2200
+ * GPP_CFGMODE_X2110
+ * GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define NB_SB_GEN2 TRUE
+
+/**
+ * @def SB_GEN2
+ * 0 - Disable
+ * 1 - Enable
+ */
+#define SB_GPP_GEN2 TRUE
+
+/**
+ * @def SB_GPP_UNHIDE_PORTS
+ * TRUE - ports visible always, even port empty
+ * FALSE - ports invisible if port empty
+ */
+#define SB_GPP_UNHIDE_PORTS FALSE
+
+/**
+ * @def GEC_CONFIG
+ * 0 - Enable
+ * 1 - Disable
+ */
+#define GEC_CONFIG 0
+
+/* set up an ACPI preferred power management profile */
+/* from acpi.h
+ * PM_UNSPECIFIED = 0,
+ * PM_DESKTOP = 1,
+ * PM_MOBILE = 2,
+ * PM_WORKSTATION = 3,
+ * PM_ENTERPRISE_SERVER = 4,
+ * PM_SOHO_SERVER = 5,
+ * PM_APPLIANCE_PC = 6,
+ * PM_PERFORMANCE_SERVER = 7,
+ * PM_TABLET = 8
+ */
+#define FADT_PM_PROFILE 6
+
+#endif
diff --git a/src/mainboard/pcengines/apu1c/romstage.c b/src/mainboard/pcengines/apu1c/romstage.c
new file mode 100755
index 0000000..106fd91
--- /dev/null
+++ b/src/mainboard/pcengines/apu1c/romstage.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+#include <cpu/x86/mtrr.h>
+#include "cpu/amd/car.h"
+#include "agesawrapper.h"
+#include <northbridge/amd/agesa/agesawrapper_call.h>
+#include <southbridge/amd/cimx/cimx_util.h>
+#include "cpu/x86/bist.h"
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct5104d/nct5104d.h>
+#include <cpu/x86/cache.h>
+#include <sb_cimx.h>
+#include "SBPLATFORM.h"
+#include "cbmem.h"
+#include "cpu/amd/mtrr.h"
+#include "cpu/amd/agesa/s3_resume.h"
+#include <southbridge/amd/cimx/sb800/gpio_oem.h>
+
+#define MSR_MTRR_VARIABLE_BASE6 0x020C
+#define MSR_MTRR_VARIABLE_MASK6 0x020D
+#define MSR_PSTATE_CONTROL 0xC0010062
+#define SERIAL_DEV PNP_DEV(0x2e, NCT5104D_SP1)
+
+#define GPIO_FTN_1 0x01
+#define GPIO_OUTPUT 0x08
+#define GPIO_INPUT 0x28
+#define GPIO_DATA_IN 0x80
+#define GPIO_DATA_LOW 0x00
+#define GPIO_DATA_HIGH 0x40
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+ msr_t msr;
+
+ /*
+ * All cores: allow caching of flash chip code and data
+ * (there are no cache-as-ram reliability concerns with family 14h)
+ */
+ msr.lo = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) & 0xFFFFFFFF;
+ msr.hi = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) >> 32;
+ wrmsr (MSR_MTRR_VARIABLE_BASE6, msr);
+
+ msr.lo = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) & 0xFFFFFFFF;
+ msr.hi = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) >> 32;
+ wrmsr (MSR_MTRR_VARIABLE_MASK6, msr);
+
+ /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
+ msr.lo = 0;
+ msr.hi = 0;
+ wrmsr (MSR_PSTATE_CONTROL, msr);
+
+ /* Init Hudson GPIOs. */
+ /* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */
+ u8 byte = pm_ioread(SB_PMIOA_REGEA);
+ byte |= 0x01;
+ pm_iowrite(SB_PMIOA_REGEA, byte);
+ /* PE3_RST# */
+ FCH_IOMUX( 10) = GPIO_FTN_1;
+ FCH_GPIO ( 10) = GPIO_OUTPUT | GPIO_DATA_HIGH;
+ /* PE4_RST# */
+ FCH_IOMUX( 11) = GPIO_FTN_1;
+ FCH_GPIO ( 11) = GPIO_OUTPUT | GPIO_DATA_HIGH;
+ /*
+ * Board revision ID
+ * GPIO15/GPIO16
+ * 00 A
+ * 01 B
+ * 10 C
+ * 11 D
+ */
+ FCH_IOMUX( 15) = GPIO_FTN_1;
+ FCH_GPIO ( 15) = GPIO_INPUT;
+ FCH_IOMUX( 16) = GPIO_FTN_1;
+ FCH_GPIO ( 16) = GPIO_INPUT;
+ /* reserved (TP13) */
+ FCH_IOMUX( 17) = GPIO_FTN_1;
+ FCH_GPIO ( 17) = GPIO_INPUT;
+ /* reserved (TP10) */
+ FCH_IOMUX( 18) = GPIO_FTN_1;
+ FCH_GPIO ( 18) = GPIO_INPUT;
+ /* MODESW# */
+ FCH_IOMUX(187) = GPIO_FTN_1;
+ FCH_GPIO (187) = GPIO_INPUT;
+ /* LED1# */
+ FCH_IOMUX(189) = GPIO_FTN_1;
+ FCH_GPIO (189) = GPIO_OUTPUT | GPIO_DATA_LOW;
+ /* LED2# */
+ FCH_IOMUX(190) = GPIO_FTN_1;
+ FCH_GPIO (190) = GPIO_OUTPUT | GPIO_DATA_LOW;
+ /* LED3# */
+ FCH_IOMUX(191) = GPIO_FTN_1;
+ FCH_GPIO (191) = GPIO_OUTPUT | GPIO_DATA_LOW;
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ sb_Poweron_Init();
+
+ post_code(0x31);
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x35);
+ AGESAWRAPPER(amdinitmmio);
+
+ post_code(0x37);
+ AGESAWRAPPER(amdinitreset);
+
+ post_code(0x39);
+ AGESAWRAPPER(amdinitearly);
+
+ int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
+ if (!s3resume) {
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+
+ post_code(0x42);
+ AGESAWRAPPER(amdinitenv);
+
+ } else { /* S3 detect */
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ AGESAWRAPPER(amdinitresume);
+
+ AGESAWRAPPER(amds3laterestore);
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ post_code(0x50);
+ copy_and_run();
+ printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
+
+ post_code(0x54); /* Should never see this post code. */
+}
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