[coreboot-gerrit] New patch to review for coreboot: af44c18 t124: Skip PLLP init to 408MHz

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7415

-gerrit

commit af44c18f44671c3b73fe855ff900a08fa0745223
Author: Jimmy Zhang <jimmzhang at nvidia.com>
Date:   Wed Mar 5 11:12:25 2014 -0800

    t124: Skip PLLP init to 408MHz
    
    PLLP is configured to 408MHz by hardware on T124. Init PLLP is needed only when
    to configure it other than 408MHz.
    
    BUG=none
    TEST=build nyan and boot kernel.
    
    Original-Change-Id: I8b1abf510ab886e7fddea8864a6d36f12529880e
    Original-Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/188849
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    (cherry picked from commit d32124cb7562cbce1bb929c3e5f238b13a27b752)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I617f77444a8dd97b20763b50066a1298d3b97724
---
 src/soc/nvidia/tegra124/clock.c | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index 9f37ed6..c292355 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -87,17 +87,18 @@ union __attribute__((transparent_union)) pll_fields {
 struct {
 	int khz;
 	struct pllcx_dividers	pllx;	/* target:  CONFIG_PLLX_KHZ */
-	struct pllpad_dividers	pllp;	/* target:  408 MHz */
 	struct pllcx_dividers	pllc;	/* target:  600 MHz */
 	struct pllpad_dividers	plld;	/* target:  925 MHz */
 	struct pllu_dividers	pllu;	/* target;  960 MHz */
 	struct pllcx_dividers	plldp;	/* target;  270 MHz */
 	struct pllcx_dividers	plld2;	/* target;  570 MHz */
+	/* Based on T124 TRM (to be updatd), PLLP is set to 408MHz in HW.
+	 * Unless configuring PLLP to a frequency other than 408MHz,
+	 * software configuration on PLLP is unneeded. */
 } static const osc_table[16] = {
 	[OSC_FREQ_OSC12]{
 		.khz = 12000,
 		.pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m =  1, .p = 0},
-		.pllp = {.n = 408, .m = 12, .p = 0, .cpcon = 8},
 		.pllc = {.n =  50, .m =  1, .p = 0},
 		.plld = {.n = 283, .m = 12, .p = 0, .cpcon = 8}, /* 283 MHz */
 		.pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2},
@@ -107,7 +108,6 @@ struct {
 	[OSC_FREQ_OSC13]{
 		.khz = 13000,
 		.pllx = {.n = TEGRA_PLLX_KHZ / 13000, .m =  1, .p = 0},
-		.pllp = {.n = 408, .m = 13, .p = 0, .cpcon = 8},
 		.pllc = {.n = 231, .m =  5, .p = 0},		/* 600.6 MHz */
 		.plld = {.n = 283, .m = 13, .p = 0, .cpcon = 8}, /* 283 MHz*/
 		.pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12, .lfcon = 2},
@@ -117,7 +117,6 @@ struct {
 	[OSC_FREQ_OSC16P8]{
 		.khz = 16800,
 		.pllx = {.n = TEGRA_PLLX_KHZ / 16800, .m =  1, .p = 0},
-		.pllp = {.n = 170, .m =  7, .p = 0, .cpcon = 4},
 		.pllc = {.n = 250, .m =  7, .p = 0},
 		.plld = {.n = 286, .m = 17, .p = 0, .cpcon = 8}, /* 282.6 MHz*/
 		.pllu = {.n = 400, .m =  7, .p = 0, .cpcon = 5, .lfcon = 2},
@@ -127,7 +126,6 @@ struct {
 	[OSC_FREQ_OSC19P2]{
 		.khz = 19200,
 		.pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m =  1, .p = 0},
-		.pllp = {.n =  85, .m =  4, .p = 0, .cpcon = 3},
 		.pllc = {.n = 125, .m =  4, .p = 0},
 		.plld = {.n = 251, .m = 17, .p = 0, .cpcon = 8}, /* 283.5 MHz */
 		.pllu = {.n = 200, .m =  4, .p = 0, .cpcon = 3, .lfcon = 2},
@@ -137,7 +135,6 @@ struct {
 	[OSC_FREQ_OSC26]{
 		.khz = 26000,
 		.pllx = {.n = TEGRA_PLLX_KHZ / 26000, .m =  1, .p = 0},
-		.pllp = {.n = 204, .m = 13, .p = 0, .cpcon = 5},
 		.pllc = {.n =  23, .m =  1, .p = 0},		   /* 598 MHz */
 		.plld = {.n = 283, .m = 26, .p = 0, .cpcon = 8}, /* 283 MHz */
 		.pllu = {.n = 960, .m = 26, .p = 0, .cpcon = 12, .lfcon = 2},
@@ -151,7 +148,6 @@ struct {
 		 * should match the 19.2MHz values.
 		 */
 		.pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m =  1, .p = 0},
-		.pllp = {.n =  85, .m =  4, .p = 0, .cpcon = 3},
 		.pllc = {.n = 125, .m =  4, .p = 0},
 		.plld = {.n = 125, .m = 17, .p = 0, .cpcon = 8}, /* 282.4 MHz */
 		.pllu = {.n = 200, .m =  4, .p = 0, .cpcon = 3, .lfcon = 2},
@@ -165,7 +161,6 @@ struct {
 		 * should match the 12MHz values.
 		 */
 		.pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m =  1, .p = 0},
-		.pllp = {.n =  24, .m =  1, .p = 0, .cpcon = 2},
 		.pllc = {.n =  50, .m =  1, .p = 0},
 		.plld = {.n = 71, .m = 12, .p = 0, .cpcon = 8}, /* 284 MHz */
 		.pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2},
@@ -517,12 +512,6 @@ void clock_init(void)
 	init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc,
 		osc_table[osc].pllx, PLLPAXS_MISC_LOCK_ENABLE);
 
-	/* init pllp */
-	init_pll(&clk_rst->pllp_base, &clk_rst->pllp_misc,
-		osc_table[osc].pllp, PLLPAXS_MISC_LOCK_ENABLE);
-	/* Set additional bit for pllp: enable override */
-	setbits_le32(&clk_rst->pllp_base, PLL_BASE_OVRRIDE);
-
 	/* init pllu */
 	init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc,
 		osc_table[osc].pllu, PLLUD_MISC_LOCK_ENABLE);