[coreboot-gerrit] Patch set updated for coreboot: 67e6325 nyan: nyan_big: Mark the address range covering the SRAM as cachable.

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7407

-gerrit

commit 67e63251d500e43fa77700fabd18f127ecf3805e
Author: Gabe Black <gabeblack at google.com>
Date:   Sat Mar 1 03:27:00 2014 -0800

    nyan: nyan_big: Mark the address range covering the SRAM as cachable.
    
    The SRAM is very likely faster than going all the way out to DRAM for data,
    but I don't think it's part of the cores themselves and won't be as fast as
    the L1 caches. Enabling caching for this region reduces the time it takes to
    get to the payload by about 75% when serial output is disabled and the main
    part of display init is commented out.
    
    BUG=chrome-os-partner:25467
    TEST=Built and booted on nyan.
    BRANCH=None
    
    Original-Change-Id: I7ff26dea9d50e7d9a76e598e5654488481286b35
    Original-Signed-off-by: Gabe Black <gabeblack at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/188459
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
    Original-Reviewed-by: Hung-Te Lin <hungte at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Tested-by: Gabe Black <gabeblack at chromium.org>
    Original-Commit-Queue: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit ac8b9b30490d511ca1b207af6845d50e08ac130f)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: If79dcd1b116f30b778788ba4fd45d362ff5d8e6e
---
 src/mainboard/google/nyan/romstage.c     | 6 ++++++
 src/mainboard/google/nyan_big/romstage.c | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 28827c8..175eb6f 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -89,10 +89,16 @@ static void __attribute__((noinline)) romstage(void)
 	u32 dram_size = dram_end - dram_start;
 
 	mmu_init();
+	/* Device memory below DRAM is uncached. */
 	mmu_config_range(0, dram_start, DCACHE_OFF);
+	/* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
+	mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
+	/* DRAM is cached. */
 	mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
+	/* A window for DMA is uncached. */
 	mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
 			 CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+	/* The space above DRAM is uncached. */
 	if (dram_end < 4096)
 		mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
 	mmu_disable_range(0, 1);
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index 0fbe316..51f5a49 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -89,10 +89,16 @@ static void __attribute__((noinline)) romstage(void)
 	u32 dram_size = dram_end - dram_start;
 
 	mmu_init();
+	/* Device memory below DRAM is uncached. */
 	mmu_config_range(0, dram_start, DCACHE_OFF);
+	/* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
+	mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
+	/* DRAM is cached. */
 	mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
+	/* A window for DMA is uncached. */
 	mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
 			 CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+	/* The space above DRAM is uncached. */
 	if (dram_end < 4096)
 		mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
 	mmu_disable_range(0, 1);