[coreboot-gerrit] Patch set updated for coreboot: 16db556 tegra124: enable JTAG in Security Mode

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7403

-gerrit

commit 16db5565d597ca3a7869c039b20017d5f51ddc6c
Author: Jimmy Zhang <jimmzhang at nvidia.com>
Date:   Tue Feb 11 17:21:20 2014 -0800

    tegra124: enable JTAG in Security Mode
    
    Once SECURITY_MODE fuse is burned, JTAG is disabled by default.
    To reenable JTAG, besides chip unique id and SecureJtagControl need
    to be built into BCT, Jtag enable flag is also needed to be set.
    
    BUG=None
    TEST=Burn SECURITY_MODE fuse, build chip specific BCT, coreboot
         comes up and jtag hooks up fine.
    
    Original-Change-Id: Ic6b61be2c09b15541400f9766d486a4fcef192a8
    Original-Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/186031
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    (cherry picked from commit ff962b81f424c840ef171d4287a65ab79b018a28)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I14b496932dbc0ed184a2212a5b33d740e1f34a4e
---
 src/soc/nvidia/tegra/apbmisc.c       | 29 +++++++++++++++++++++++++++++
 src/soc/nvidia/tegra/apbmisc.h       | 35 +++++++++++++++++++++++++++++++++++
 src/soc/nvidia/tegra124/Makefile.inc |  1 +
 src/soc/nvidia/tegra124/bootblock.c  |  4 ++++
 4 files changed, 69 insertions(+)

diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c
new file mode 100644
index 0000000..fea10b5
--- /dev/null
+++ b/src/soc/nvidia/tegra/apbmisc.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/addressmap.h>
+
+#include "apbmisc.h"
+
+void enable_jtag(void)
+{
+	struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE;
+	write32(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl);
+}
diff --git a/src/soc/nvidia/tegra/apbmisc.h b/src/soc/nvidia/tegra/apbmisc.h
new file mode 100644
index 0000000..805d0bf
--- /dev/null
+++ b/src/soc/nvidia/tegra/apbmisc.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA_APBMISC_H__
+#define __SOC_NVIDIA_TEGRA_APBMISC_H__
+
+#include <stdint.h>
+
+struct apbmisc {
+	u32 reserved0[9];		/* ABP_MISC_PP_ offsets 00-20 */
+	u32 pp_config_ctl;		/* _CONFIG_CTL_0, offset 24 */
+};
+
+#define PP_CONFIG_CTL_TBE		(1 << 7)
+#define PP_CONFIG_CTL_JTAG		(1 << 6)
+
+void enable_jtag(void);
+
+#endif	/* __SOC_NVIDIA_TEGRA_APBMISC_H__ */
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 4ba2342..07184f8 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -13,6 +13,7 @@ bootblock-y += ../tegra/gpio.c
 bootblock-y += ../tegra/i2c.c
 bootblock-y += ../tegra/pingroup.c
 bootblock-y += ../tegra/pinmux.c
+bootblock-y += ../tegra/apbmisc.c
 bootblock-y += timer.c
 ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
 bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c
diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index 0e10a2b..22024af 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -23,6 +23,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <soc/clock.h>
+#include <soc/nvidia/tegra/apbmisc.h>
 
 #include "pinmux.h"
 #include "power.h"
@@ -31,6 +32,9 @@ void main(void)
 {
 	void *entry;
 
+	// enable JTAG at the earliest stage
+	enable_jtag();
+
 	clock_early_uart();
 
 	// Serial out, tristate off.