[coreboot-gerrit] Patch merged into coreboot/master: b9a4b71 nyan: nyan_big: Mark the address range covering the SRAM as cachable.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit b9a4b713f88c111628d3b35d8a695de88ff39ecd
Author: Gabe Black <gabeblack at google.com>
Date:   Sat Mar 1 03:27:00 2014 -0800

    nyan: nyan_big: Mark the address range covering the SRAM as cachable.
    
    The SRAM is very likely faster than going all the way out to DRAM for data,
    but I don't think it's part of the cores themselves and won't be as fast as
    the L1 caches. Enabling caching for this region reduces the time it takes to
    get to the payload by about 75% when serial output is disabled and the main
    part of display init is commented out.
    
    BUG=chrome-os-partner:25467
    TEST=Built and booted on nyan.
    BRANCH=None
    
    Original-Change-Id: I7ff26dea9d50e7d9a76e598e5654488481286b35
    Original-Signed-off-by: Gabe Black <gabeblack at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/188459
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
    Original-Reviewed-by: Hung-Te Lin <hungte at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Tested-by: Gabe Black <gabeblack at chromium.org>
    Original-Commit-Queue: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit ac8b9b30490d511ca1b207af6845d50e08ac130f)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: If79dcd1b116f30b778788ba4fd45d362ff5d8e6e
    Reviewed-on: http://review.coreboot.org/7407
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix at chromium.org>


See http://review.coreboot.org/7407 for details.

-gerrit