[coreboot-gerrit] Patch merged into coreboot/master: c225e4c t124: nyan: Enable lock bit on pll

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c225e4c3350f1ec477478ec376924a098c961ddb
Author: Jimmy Zhang <jimmzhang at nvidia.com>
Date:   Fri Feb 28 17:35:48 2014 -0800

    t124: nyan: Enable lock bit on pll
    
    A PLL (Phase-Locked Loop) clock must be locked before it is assigned
    as clock source. Otherwise, this clock is unreliable.
    
    Before:
    c base(60006080): 48003201, misc(6000608c): 03000000
    x base(600060e0): 40009e01, misc(600060e4): 00000000
    p base(600060a0): 40002201, misc(600060ac): 00000200
    u base(600060c0): 40005001, misc(600060cc): 00000300
    d base(600060d0): 48011b0c, misc(600060dc): 40400800
    dp base(60006590): 58305a01, misc(60006594): 40000000
    
    After:
    c base(60006080): 48003201, misc(6000608c): 03000000
    x base(600060e0): 48009e01, misc(600060e4): 00040000
    p base(600060a0): 5801980c, misc(600060ac): 00040800
    u base(600060c0): 48005001, misc(600060cc): 00400300
    d base(600060d0): 48011b0c, misc(600060dc): 40400800
    dp base(60006590): 58305a01, misc(60006594): 40000000
    
    BUG=None
    TEST=build nyan and boot
    
    Original-Change-Id: I7e5a2eeb5b17f761e0c462ec68a8b221f327fedc
    Original-Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/188447
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    (cherry picked from commit 7e8e2854b2b7d1ed20d74891c3d19b6c3dd41c55)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Ief9efa6937af26fe1a10a7b360fc2f5477416b97
    Reviewed-on: http://review.coreboot.org/7414
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix at chromium.org>


See http://review.coreboot.org/7414 for details.

-gerrit