[coreboot-gerrit] Patch set updated for coreboot: 7e9cbaa fsp_baytrail: update for UPD_DEFAULT_CHECK macro
Martin Roth (gaumless@gmail.com)
gerrit at coreboot.org
Mon Nov 17 05:53:27 CET 2014
Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7488
-gerrit
commit 7e9cbaa0009b0baab133f6bd0322314ab2926cc0
Author: Martin Roth <martin.roth at se-eng.com>
Date: Sun Nov 16 20:06:23 2014 -0700
fsp_baytrail: update for UPD_DEFAULT_CHECK macro
- Update chipset_fsp_util.c to use the UPD_DEFAULT_CHECK macro. This
makes the code more standardized and easier to read.
- Update chip.h to use standardized macros
Change-Id: Icbe5ec92b0aa31e21f3dd1593a96b246d83008f7
Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
src/soc/intel/fsp_baytrail/chip.h | 95 ++++++++++++-----------
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 33 +++-----
2 files changed, 59 insertions(+), 69 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h
index 12eba10..b2723c3 100644
--- a/src/soc/intel/fsp_baytrail/chip.h
+++ b/src/soc/intel/fsp_baytrail/chip.h
@@ -22,6 +22,7 @@
#define _FSP_BAYTRAIL_CHIP_H_
#include <arch/acpi.h>
+#include <drivers/intel/fsp/fsp_values.h>
/* The devicetree parser expects chip.h to reside directly in the path
* specified by the devicetree. */
@@ -33,8 +34,8 @@ struct soc_intel_fsp_baytrail_config {
/* Spd addresses */
uint8_t PcdMrcInitSPDAddr1;
uint8_t PcdMrcInitSPDAddr2;
- #define SPD_ADDR_DEFAULT 0x00
- #define SPD_ADDR_DISABLED 0xFF
+ #define SPD_ADDR_DEFAULT UPD_SPD_ADDR_DEFAULT
+ #define SPD_ADDR_DISABLED UPD_SPD_ADDR_DISABLED
/* SataMode
* NOTE: These are offset by 1 to set 0 as "use default". This is so that
@@ -45,9 +46,9 @@ struct soc_intel_fsp_baytrail_config {
* 0x1 "AHCI"
*/
uint8_t PcdSataMode;
- #define SATA_MODE_DEFAULT 0x00
- #define SATA_MODE_IDE 0x01
- #define SATA_MODE_AHCI 0x02
+ #define SATA_MODE_DEFAULT UPD_DEFAULT
+ #define SATA_MODE_IDE INCREMENT_FOR_DEFAULT(0)
+ #define SATA_MODE_AHCI INCREMENT_FOR_DEFAULT(0)
/*
* MrcInitTsegSize
@@ -57,11 +58,11 @@ struct soc_intel_fsp_baytrail_config {
* 0x08, "8 MB"
*/
uint16_t PcdMrcInitTsegSize;
- #define TSEG_SIZE_DEFAULT 0
- #define TSEG_SIZE_1_MB 1
- #define TSEG_SIZE_2_MB 2
- #define TSEG_SIZE_4_MB 4
- #define TSEG_SIZE_8_MB 8
+ #define TSEG_SIZE_DEFAULT UPD_DEFAULT
+ #define TSEG_SIZE_1_MB INCREMENT_FOR_DEFAULT(1)
+ #define TSEG_SIZE_2_MB INCREMENT_FOR_DEFAULT(2)
+ #define TSEG_SIZE_4_MB INCREMENT_FOR_DEFAULT(4)
+ #define TSEG_SIZE_8_MB INCREMENT_FOR_DEFAULT(8)
/*
* MrcInitMmioSize
@@ -70,10 +71,10 @@ struct soc_intel_fsp_baytrail_config {
* 0x800, "2.0 GB"
*/
uint16_t PcdMrcInitMmioSize;
- #define MMIO_SIZE_DEFAULT 0x00
- #define MMIO_SIZE_1_0_GB 0x400
- #define MMIO_SIZE_1_5_GB 0x600
- #define MMIO_SIZE_2_0_GB 0x800
+ #define MMIO_SIZE_DEFAULT UPD_DEFAULT
+ #define MMIO_SIZE_1_0_GB INCREMENT_FOR_DEFAULT(0x400)
+ #define MMIO_SIZE_1_5_GB INCREMENT_FOR_DEFAULT(0x600)
+ #define MMIO_SIZE_2_0_GB INCREMENT_FOR_DEFAULT(0x800)
/*
* eMMCBootMode
@@ -87,12 +88,12 @@ struct soc_intel_fsp_baytrail_config {
* 0x3 "eMMC 4.5"
*/
uint8_t PcdeMMCBootMode;
- #define EMMC_USE_DEFAULT 0
- #define EMMC_DISABLED 1
- #define EMMC_AUTO 2
- #define EMMC_4_1 3
- #define EMMC_4_5 4
- #define EMMC_FOLLOWS_DEVICETREE 5
+ #define EMMC_USE_DEFAULT UPD_DEFAULT
+ #define EMMC_DISABLED UPD_DISABLE
+ #define EMMC_AUTO INCREMENT_FOR_DEFAULT(1)
+ #define EMMC_4_1 INCREMENT_FOR_DEFAULT(2)
+ #define EMMC_4_5 INCREMENT_FOR_DEFAULT(3)
+ #define EMMC_FOLLOWS_DEVICETREE UPD_USE_DEVICETREE
/*
* IgdDvmt50PreAlloc
@@ -114,23 +115,23 @@ struct soc_intel_fsp_baytrail_config {
* 0x10, "512 MB"
*/
uint8_t PcdIgdDvmt50PreAlloc;
- #define IGD_MEMSIZE_DEFAULT 0x00
- #define IGD_MEMSIZE_32MB 0x01
- #define IGD_MEMSIZE_64MB 0x02
- #define IGD_MEMSIZE_96MB 0x03
- #define IGD_MEMSIZE_128MB 0x04
- #define IGD_MEMSIZE_160MB 0x05
- #define IGD_MEMSIZE_192MB 0x06
- #define IGD_MEMSIZE_224MB 0x07
- #define IGD_MEMSIZE_256MB 0x08
- #define IGD_MEMSIZE_288MB 0x09
- #define IGD_MEMSIZE_320MB 0x0A
- #define IGD_MEMSIZE_352MB 0x0B
- #define IGD_MEMSIZE_384MB 0x0C
- #define IGD_MEMSIZE_416MB 0x0D
- #define IGD_MEMSIZE_448MB 0x0E
- #define IGD_MEMSIZE_480MB 0x0F
- #define IGD_MEMSIZE_512MB 0x10
+ #define IGD_MEMSIZE_DEFAULT UPD_DEFAULT
+ #define IGD_MEMSIZE_32MB INCREMENT_FOR_DEFAULT(0x01)
+ #define IGD_MEMSIZE_64MB INCREMENT_FOR_DEFAULT(0x02)
+ #define IGD_MEMSIZE_96MB INCREMENT_FOR_DEFAULT(0x03)
+ #define IGD_MEMSIZE_128MB INCREMENT_FOR_DEFAULT(0x04)
+ #define IGD_MEMSIZE_160MB INCREMENT_FOR_DEFAULT(0x05)
+ #define IGD_MEMSIZE_192MB INCREMENT_FOR_DEFAULT(0x06)
+ #define IGD_MEMSIZE_224MB INCREMENT_FOR_DEFAULT(0x07)
+ #define IGD_MEMSIZE_256MB INCREMENT_FOR_DEFAULT(0x08)
+ #define IGD_MEMSIZE_288MB INCREMENT_FOR_DEFAULT(0x09)
+ #define IGD_MEMSIZE_320MB INCREMENT_FOR_DEFAULT(0x0A)
+ #define IGD_MEMSIZE_352MB INCREMENT_FOR_DEFAULT(0x0B)
+ #define IGD_MEMSIZE_384MB INCREMENT_FOR_DEFAULT(0x0C)
+ #define IGD_MEMSIZE_416MB INCREMENT_FOR_DEFAULT(0x0D)
+ #define IGD_MEMSIZE_448MB INCREMENT_FOR_DEFAULT(0x0E)
+ #define IGD_MEMSIZE_480MB INCREMENT_FOR_DEFAULT(0x0F)
+ #define IGD_MEMSIZE_512MB INCREMENT_FOR_DEFAULT(0x10)
#define IGD_MEMSIZE_MULTIPLIER 32
/*
@@ -139,10 +140,10 @@ struct soc_intel_fsp_baytrail_config {
* Selection 0x3 , "512 MB"
*/
uint8_t PcdApertureSize;
- #define APERTURE_SIZE_DEFAULT 0
- #define APERTURE_SIZE_128MB 1
- #define APERTURE_SIZE_256MB 2
- #define APERTURE_SIZE_512MB 3
+ #define APERTURE_SIZE_DEFAULT UPD_DEFAULT
+ #define APERTURE_SIZE_128MB INCREMENT_FOR_DEFAULT(1)
+ #define APERTURE_SIZE_256MB INCREMENT_FOR_DEFAULT(2)
+ #define APERTURE_SIZE_512MB INCREMENT_FOR_DEFAULT(3)
#define APERTURE_SIZE_BASE 64
/*
@@ -150,18 +151,18 @@ struct soc_intel_fsp_baytrail_config {
* Selection 0x2 , "2 MB"
*/
uint8_t PcdGttSize;
- #define GTT_SIZE_DEFAULT 0
- #define GTT_SIZE_1MB 1
- #define GTT_SIZE_2MB 2
+ #define GTT_SIZE_DEFAULT UPD_DEFAULT
+ #define GTT_SIZE_1MB INCREMENT_FOR_DEFAULT(1)
+ #define GTT_SIZE_2MB INCREMENT_FOR_DEFAULT(2)
/*
* Enable PCI Mode for LPSS SIO devices.
* If disabled, LPSS SIO devices will run in ACPI mode.
*/
uint8_t PcdLpssSioEnablePciMode;
- #define LPSS_PCI_MODE_DEFAULT 0x00
- #define LPSS_PCI_MODE_DISABLE 0x01
- #define LPSS_PCI_MODE_ENABLE 0x02
+ #define LPSS_PCI_MODE_DEFAULT UPD_DEFAULT
+ #define LPSS_PCI_MODE_DISABLE UPD_DISABLE
+ #define LPSS_PCI_MODE_ENABLE UPD_ENABLE
/* modifiers for various enables */
uint8_t AzaliaAutoEnable;
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index 2a41e61..b74707b 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -94,38 +94,27 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
UpdData->PcdMrcInitSPDAddr2 = config->PcdMrcInitSPDAddr2;
printk(BIOS_DEBUG, "SPD Addr2:\t\t0x%02x\n", UpdData->PcdMrcInitSPDAddr2);
- if (config->PcdSataMode != SATA_MODE_DEFAULT)
- UpdData->PcdSataMode = config->PcdSataMode - SATA_MODE_IDE;
+ UPD_DEFAULT_CHECK(PcdSataMode);
+ UPD_DEFAULT_CHECK(PcdLpssSioEnablePciMode);
+ UPD_DEFAULT_CHECK(PcdMrcInitMmioSize);
+ UPD_DEFAULT_CHECK(PcdIgdDvmt50PreAlloc);
+ UPD_DEFAULT_CHECK(PcdApertureSize);
+ UPD_DEFAULT_CHECK(PcdGttSize);
if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT) ||
(config->PcdeMMCBootMode != EMMC_FOLLOWS_DEVICETREE))
UpdData->PcdeMMCBootMode = config->PcdeMMCBootMode;
- if (config->PcdLpssSioEnablePciMode != LPSS_PCI_MODE_DEFAULT)
- UpdData->PcdLpssSioEnablePciMode = config->PcdLpssSioEnablePciMode -
- LPSS_PCI_MODE_DISABLE;
-
if (config->PcdMrcInitTsegSize != TSEG_SIZE_DEFAULT)
UpdData->PcdMrcInitTsegSize = config->PcdMrcInitTsegSize;
- printk(BIOS_DEBUG, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize);
-
- if (config->PcdMrcInitMmioSize != MMIO_SIZE_DEFAULT)
- UpdData->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize;
- printk(BIOS_DEBUG, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize);
-
- if (config->PcdIgdDvmt50PreAlloc != IGD_MEMSIZE_DEFAULT)
- UpdData->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc;
- printk(BIOS_DEBUG, "IGD Memory Size:\t%d MB\n",
- UpdData->PcdIgdDvmt50PreAlloc * IGD_MEMSIZE_MULTIPLIER);
- if (config->PcdApertureSize != APERTURE_SIZE_DEFAULT)
- UpdData->PcdApertureSize = config->PcdApertureSize;
+ printk(BIOS_DEBUG, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize);
+ printk(BIOS_DEBUG, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize);
printk(BIOS_DEBUG, "Aperture Size:\t\t%d MB\n",
APERTURE_SIZE_BASE << UpdData->PcdApertureSize);
-
- if (config->PcdGttSize != GTT_SIZE_DEFAULT)
- UpdData->PcdGttSize = config->PcdGttSize;
- printk(BIOS_DEBUG, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize);
+ printk(BIOS_DEBUG, "IGD Memory Size:\t%d MB\n",
+ UpdData->PcdIgdDvmt50PreAlloc * IGD_MEMSIZE_MULTIPLIER);
+ printk(BIOS_DEBUG, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize);
/* Advance dev to PCI device 0.0 */
for (dev = &dev_root; dev; dev = dev_find_next_pci_device(dev)){
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