[coreboot-gerrit] New patch to review for coreboot: 09ccbf1 Add new microcode update

[Herve ELTER (rvnvv2@gmail.com)]

Herve ELTER (rvnvv2 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7522

-gerrit

commit 09ccbf13a5f7ded178d5e34e295614465e290420
Author: Herve <rvnvv74 at gmail.com>
Date:   Wed Nov 19 15:43:57 2014 +0100

    Add new microcode update
    
    New microcode for Baytrail D0 stepping
    
    Change-Id: I5b6139c42a19d2b73ad3a9302f701520288d87a9
    Signed-off-by: Herve <rvnvv74 at gmail.com>
---
 src/soc/intel/fsp_baytrail/Kconfig                    | 2 +-
 src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index e9391c3..a019469 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -104,7 +104,7 @@ config CPU_MICROCODE_CBFS_LOC
 
 config CPU_MICROCODE_CBFS_LEN
 	hex
-	default 0x19800
+	default 0x26400
 	help
 	  This should be updated when the microcode patch changes.
 
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
index 43cbf00..ce0a67d 100644
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
@@ -19,8 +19,9 @@
 
 unsigned microcode[] = {
 
-/* Size is 0x19800 - update in Kconfig when the patch gets updated. */
+/* Size is 0x26400 - update in Kconfig when the patch gets updated. */
 #include "M0230672228.h"  // M0230672: Baytrail "Super SKU" B0/B1
 #include "M013067331E.h"  // M0130673: Baytrail I B2 / B3
+#include "M0130679902.h"  // M0130679: Baytrail I D0
 
 };