[coreboot-gerrit] New patch to review for coreboot: c1b74ae AGESA fam15: Move LPC decode enable for serial port

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7601

-gerrit

commit c1b74ae3ba5d7aed01bbbb4263f29fa3ba5b23b3
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Nov 21 17:40:37 2014 +0200

    AGESA fam15: Move LPC decode enable for serial port
    
    Move LPC decode enable out of agesawrapper.c. It should not be on the
    execution path of AP CPUs and function is not related to AGESA per se.
    
    Change-Id: I19c6a9c7d71c9899fdc898c09c337d747424fcec
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/mainboard/tyan/s8226/agesawrapper.c | 7 -------
 src/mainboard/tyan/s8226/romstage.c     | 4 ++++
 2 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c
index 36aa35a..0600f89 100644
--- a/src/mainboard/tyan/s8226/agesawrapper.c
+++ b/src/mainboard/tyan/s8226/agesawrapper.c
@@ -176,8 +176,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 {
 	AGESA_STATUS                  Status;
 	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/*
@@ -194,11 +192,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
 	MsrReg = MsrReg | 0x0000400000000000;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
 
-	/* For serial port */
-	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index e7a808e..a0e8bfd 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -47,6 +47,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
 	post_code(0x31);
 
+	/* For serial port. */
+	device_t dev = PCI_DEV(0, 0x14, 3);
+	pci_write_config32(dev, 0x44, 0xff03ffd5);
+
 	/* Halt if there was a built in self test failure */
 	post_code(0x33);
 	report_bist_failure(bist);