[coreboot-gerrit] New patch to review for coreboot: wakeup: Switch back to 32bit mode first

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11106

-gerrit

commit 4eddcf7fe77b1b60315b9baa30bb955544d87475
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Jul 31 16:46:28 2015 -0700

    wakeup: Switch back to 32bit mode first
    
    On x86_64 we need to leave long mode before we can switch to 16bit
    mode. Oh joy! When's my 64bit resume pointer coming?
    
    Why didn't this get caught earlier? Seems the Asrock E350M2 didn't
    do Suspend/Resume?
    
    Yes, I know it's Intel syntax. Will be converted to AT&T syntax
    as soon as the whole thing actually works.. 8)
    
    Change-Id: Ic51869cf67d842041f8842cd9964d72a024c335f
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 src/arch/x86/wakeup.S | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S
index 38d6ea4..acc8737 100644
--- a/src/arch/x86/wakeup.S
+++ b/src/arch/x86/wakeup.S
@@ -32,6 +32,34 @@
 
 	.globl __wakeup
 __wakeup:
+#ifdef __x86_64__
+	.intel_syntax noprefix
+	xor     rax,rax
+	mov     ax, ss
+	push    rax
+	mov     rax, rsp
+	add     rax, 8
+	push    rax
+	pushfq
+	push    0x10
+	lea     rax,[rip+3]
+	push    rax
+	iretq
+
+	.code32
+
+	/* disable paging */
+	mov     eax, cr0
+	btc     eax, 31
+	mov     cr0, eax
+
+	/* disable long mode */
+	mov     ecx, 0xC0000080
+	rdmsr
+	btc     eax, 8
+	wrmsr
+	.att_syntax prefix
+#endif
 	/* First prepare the jmp to the resume vector */
 	mov	0x4(%esp), %eax	/* vector */
 	/* last 4 bits of linear addr are taken as offset */