[coreboot-gerrit] New patch to review for coreboot: skylake: fix serial port with new code base
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Wed Aug 12 17:51:12 CEST 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11172
-gerrit
commit 67beeef7cc61f2617a691bf87a2f103edc77a16f
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Jul 30 16:52:56 2015 -0500
skylake: fix serial port with new code base
Many Kconfig options changed in coreboot.org since
skylake was first started. Fix Kconfig option name
changes, and also provide a common option, UART_DEBUG
that can be selected to select all the necessary
options.
Note: It's still a requirement to manually unset the
8250IO option because that's unconditionally set.
BUG=chrome-os-partner:43419
BUG=chrome-os-partner:43463
BRANCH=None
TEST=Built glados. Booted into kernel. Kernel reboots somewhere.
Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289951
Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/skylake/Kconfig | 12 ++++++---
src/soc/intel/skylake/Makefile.inc | 3 +++
src/soc/intel/skylake/include/soc/iomap.h | 3 +++
src/soc/intel/skylake/romstage/romstage.c | 2 +-
src/soc/intel/skylake/romstage/uart.c | 11 ++++++---
src/soc/intel/skylake/uart.c | 9 ++++---
src/soc/intel/skylake/uart_debug.c | 41 +++++++++++++++++++++++++++++++
7 files changed, 69 insertions(+), 12 deletions(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 92bae39..e2c43f0 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -188,12 +188,16 @@ config SMM_TSEG_SIZE
hex
default 0x800000
-config TTYS0_BASE
- hex
- default 0xfe034000
-
config VGA_BIOS_ID
string
default "8086,0406"
+config UART_DEBUG
+ bool "Enable UART debug port."
+ default y if CONSOLE_SERIAL
+ default n
+ select DRIVERS_UART
+ select DRIVERS_UART_8250MEM
+ select DRIVERS_UART_8250MEM_32
+
endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index af299c3..9fa9503 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -19,6 +19,7 @@ romstage-y += pei_data.c
romstage-y += pmutil.c
romstage-y += smbus_common.c
romstage-y += tsc_freq.c
+romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += chip.c
@@ -46,6 +47,7 @@ ramstage-y += smmrelocate.c
ramstage-y += systemagent.c
ramstage-y += tsc_freq.c
ramstage-y += uart.c
+ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c
ramstage-y += xhci.c
smm-y += cpu_info.c
@@ -57,6 +59,7 @@ smm-y += pmutil.c
smm-y += smihandler.c
smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
smm-y += tsc_freq.c
+smm-$(CONFIG_UART_DEBUG) += uart_debug.c
CPPFLAGS_common += -I$(src)/arch/x86/include/
CPPFLAGS_common += -I$(src)/soc/intel/skylake
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index c478daf..764e966 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -27,6 +27,9 @@
#define PCH_PCR_BASE_ADDRESS 0xfd000000
#define PCH_BCR_BASE_SIZE 0x1000000
+#define UART_DEBUG_BASE_ADDRESS 0xfe034000
+#define UART_DEBUG_BASE_SIZE 0x1000
+
#define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE 0x8000
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 04ffa3e..af9c78b 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -50,7 +50,7 @@ void soc_pre_console_init(struct romstage_params *params)
/* System Agent Early Initialization */
systemagent_early_init();
- if (IS_ENABLED(CONFIG_CONSOLE_UART8250MEM_32))
+ if (IS_ENABLED(CONFIG_UART_DEBUG))
pch_uart_init();
}
diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c
index afc8c63..4dad8f6 100644
--- a/src/soc/intel/skylake/romstage/uart.c
+++ b/src/soc/intel/skylake/romstage/uart.c
@@ -19,6 +19,7 @@
*/
#include <arch/io.h>
+#include <console/uart.h>
#include <device/pci_def.h>
#include <stdint.h>
#include <soc/pci_devs.h>
@@ -33,7 +34,7 @@ void pch_uart_init(void)
{
device_t dev = PCH_DEV_UART2;
u32 tmp;
- u8 *base = (u8 *)CONFIG_TTYS0_BASE;
+ u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE);
/* Set configured UART2 base address */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base);
@@ -49,7 +50,11 @@ void pch_uart_init(void)
SIO_REG_PPR_RESETS_IDMA;
write32(base + SIO_REG_PPR_RESETS, tmp);
- /* Set M and N divisor inputs and enable clock */
+ /*
+ * Set M and N divisor inputs and enable clock.
+ * Main reference frequency to UART is:
+ * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
+ */
tmp = read32(base + SIO_REG_PPR_CLOCK);
tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
(SIO_REG_PPR_CLOCK_N_DIV << 16) |
@@ -57,7 +62,7 @@ void pch_uart_init(void)
write32(base + SIO_REG_PPR_CLOCK, tmp);
/* Put UART2 in byte access mode for 16550 compatibility */
- if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32))
+ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
pcr_andthenor32(PID_SERIALIO,
R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2);
diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c
index 9304118..c93f5c0 100644
--- a/src/soc/intel/skylake/uart.c
+++ b/src/soc/intel/skylake/uart.c
@@ -18,11 +18,11 @@
* Foundation, Inc.
*/
-#include <console/uart.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h>
+#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
@@ -36,10 +36,11 @@ static void pch_uart_read_resources(struct device *dev)
pci_dev_read_resources(dev);
/* Set the configured UART base address for the debug port */
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32) &&
- pch_uart_is_debug(dev)) {
+ if (IS_ENABLED(CONFIG_UART_DEBUG) && pch_uart_is_debug(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
- res->size = 0x1000;
+ /* Need to set the base and size for the resource allocator. */
+ res->base = UART_DEBUG_BASE_ADDRESS;
+ res->size = UART_DEBUG_BASE_SIZE;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
}
diff --git a/src/soc/intel/skylake/uart_debug.c b/src/soc/intel/skylake/uart_debug.c
new file mode 100644
index 0000000..0328507
--- /dev/null
+++ b/src/soc/intel/skylake/uart_debug.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stddef.h>
+#include <console/uart.h>
+#include <soc/iomap.h>
+#include <soc/serialio.h>
+
+unsigned int uart_platform_refclk(void)
+{
+ /*
+ * Set M and N divisor inputs and enable clock.
+ * Main reference frequency to UART is:
+ * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
+ * The different order below is to handle integer math overflow.
+ */
+ return 120 * MHz / SIO_REG_PPR_CLOCK_N_DIV * SIO_REG_PPR_CLOCK_M_DIV;
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ /* Same base address for all debug port usage. In reality UART2
+ * is currently only supported. */
+ return UART_DEBUG_BASE_ADDRESS;
+}
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