[coreboot-gerrit] New patch to review for coreboot: skylake: set DISB in GEN_PMCON_A register properly
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Wed Aug 12 17:51:42 CEST 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11183
-gerrit
commit f6814c72d765fafafd9759d1077313a0b04436d3
Author: Aaron Durbin <adurbin at chromium.org>
Date: Tue Aug 4 14:04:47 2015 -0500
skylake: set DISB in GEN_PMCON_A register properly
DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM
training is complete. However, as a 8-bit write was
being performed the bit was never being set.
BUG=chrome-os-partner:43516
BRANCH=None
TEST=Built and booted to kernel. Rebooted. Noted full memory
training was not being peformed.
Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290337
Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/skylake/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index b62a288..a97f751 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -47,7 +47,7 @@ static const struct reg_script pch_pmc_misc_init_script[] = {
/* Enable SCI and clear SLP requests. */
REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
/* Indicate DRAM init done for MRC */
- REG_PCI_OR8(GEN_PMCON_A, DISB),
+ REG_PCI_OR32(GEN_PMCON_A, DISB),
REG_SCRIPT_END
};
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