[coreboot-gerrit] New patch to review for coreboot: Skylake: Add ASL code to enable GPIO controller
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Wed Aug 12 17:51:59 CEST 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11191
-gerrit
commit f8154f312127d624d3b640de6145f8a486f1816a
Author: Archana Patni <archana.patni at intel.com>
Date: Sat Jul 4 00:56:32 2015 +0530
Skylake: Add ASL code to enable GPIO controller
This patch enables GPIO controller for skylake. It adds
community base addresses and offset for Community0, Community1,
and Community3. Community2 is not exposed in BIOS or enabled
in the kernel driver.
Also, clean up the carry over GWAK implementation from BDW.
BRANCH=None
BUG=chrome-os-partner:42393
TEST=cat /sys/kernel/debug/gpio should list of GPIOs
TEST=export a GPIO pin using /sys/class/gpio/export
Original-Change-Id: I891c40589d3dbd796cf593626472c7b5674a1ae0
Original-Signed-off-by: Archana Patni <archana.patni at intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291230
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
Original-Commit-Queue: Aaron Durbin <adurbin at chromium.org>
Change-Id: I7481ce682ccae872fddf81b3188c3415d5d3f7d9
Signed-off-by: Archana Patni <archana.patni at intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha at intel.com>
---
src/soc/intel/skylake/acpi/gpio.asl | 147 +++++++++-----------------
src/soc/intel/skylake/include/soc/gpio_defs.h | 5 +
src/soc/intel/skylake/include/soc/iomap.h | 6 +-
src/soc/intel/skylake/include/soc/irq.h | 2 +
4 files changed, 57 insertions(+), 103 deletions(-)
diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl
index 69ee721..3b4740b 100644
--- a/src/soc/intel/skylake/acpi/gpio.asl
+++ b/src/soc/intel/skylake/acpi/gpio.asl
@@ -18,46 +18,64 @@
* Foundation, Inc.
*/
-Device (GPIO)
+#include <soc/irq.h>
+#include <soc/iomap.h>
+#include <soc/pcr.h>
+#include <soc/gpio_defs.h>
+
+/* PCR Register Access Methods PCR Dword Read arg0: PID arg1: Offset */
+Method (PCRR, 2, Serialized)
{
- // GPIO Controller
- Method (_HID)
+ Add (ShiftLeft (Arg0, PCR_PORTID_SHIFT), Arg1, Local0)
+ Add (PCH_PCR_BASE_ADDRESS, Local0, Local0)
+ OperationRegion (PCR0, SystemMemory, Local0, 0x4)
+
+ Field(PCR0, DWordAcc, Lock, Preserve)
{
- //Sunrisepoint-LP PCH
- Return ("INT344B")
+ Offset(0x00),
+ DAT0, 32
}
+ Return (DAT0)
+}
+
+Device (GPIO)
+{
+ /* GPIO Controller */
+ Name (_HID, "INT344B")
Name (_UID, 1)
Name (RBUF, ResourceTemplate()
{
- DWordIo (ResourceProducer,
- MinFixed, // IsMinFixed
- MaxFixed, // IsMaxFixed
- PosDecode, // Decode
- EntireRange, // ISARanges
- 0x00000000, // AddressGranularity
- 0x00000000, // AddressMinimum
- 0x00000000, // AddressMaximum
- 0x00000000, // AddressTranslation
- 0x00000000, // RangeLength
- , // ResourceSourceIndex
- , // ResourceSource
- BAR0)
- // Disabled due to IRQ storm: http://crosbug.com/p/29548
- //Interrupt (ResourceConsumer,
- // Level, ActiveHigh, Shared, , , ) {14}
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R0)
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R1)
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R3)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _R4)
+ {
+ GPIO_IRQ14,
+ }
})
- Method (_CRS, 0, NotSerialized)
+ Method (_CRS, 0, NotSerialized) /* _CRS: Current Resource Settings */
{
- CreateDwordField (^RBUF, ^BAR0._MIN, BMIN)
- CreateDwordField (^RBUF, ^BAR0._MAX, BMAX)
- CreateDwordField (^RBUF, ^BAR0._LEN, BLEN)
-
- Store (GPIO_BASE_SIZE, BLEN)
- Store (GPIO_BASE_ADDRESS, BMIN)
- Store (Subtract (Add (GPIO_BASE_ADDRESS,
- GPIO_BASE_SIZE), 1), BMAX)
+ CreateDWordField (^RBUF, ^_R0._BAS, COM0)
+ CreateDWordField (^RBUF, ^_R1._BAS, COM1)
+ CreateDWordField (^RBUF, ^_R3._BAS, COM3)
+ CreateDWordField (^RBUF, ^_R4._INT, IRQN)
+
+ Store (Add (PCH_PCR_BASE_ADDRESS,
+ ShiftLeft (PID_GPIOCOM0, PCR_PORTID_SHIFT)), COM0)
+ Store (Add (PCH_PCR_BASE_ADDRESS,
+ ShiftLeft (PID_GPIOCOM1, PCR_PORTID_SHIFT)), COM1)
+ Store (Add (PCH_PCR_BASE_ADDRESS,
+ ShiftLeft (PID_GPIOCOM3, PCR_PORTID_SHIFT)), COM3)
+ Store (And (PCRR (PID_GPIOCOM0, MISCCFG_OFFSET),
+ GPIO_DRIVER_IRQ_ROUTE_MASK), Local0)
+
+ If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) {
+ Store (GPIO_IRQ14, IRQN)
+ } Else {
+ Store (GPIO_IRQ15, IRQN)
+ }
Return (RBUF)
}
@@ -66,73 +84,4 @@ Device (GPIO)
{
Return (0xF)
}
-
- // GWAK: Setup GPIO as ACPI GPE for Wake
- // Arg0: GPIO Number
- Method (GWAK, 1, NotSerialized)
- {
- // Local0 = GPIO Base Address
- Store (And (GPBS, Not(0x1)), Local0)
-
- // Local1 = BANK, Local2 = OFFSET
- Divide (Arg0, 32, Local2, Local1)
-
- //
- // Set OWNER to ACPI
- //
-
- // Local3 = GPIOBASE + GPIO_OWN(BANK)
- Store (Add (Local0, Multiply (Local1, 0x4)), Local3)
-
- // GPIO_OWN(BANK)
- OperationRegion (IOWN, SystemIO, Local3, 4)
- Field (IOWN, AnyAcc, NoLock, Preserve) {
- GOWN, 32,
- }
-
- // GPIO_OWN[GPIO] = 0 (ACPI)
- Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN)
-
- //
- // Set ROUTE to SCI
- //
-
- // Local3 = GPIOBASE + GPIO_ROUTE(BANK)
- Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3)
-
- // GPIO_ROUTE(BANK)
- OperationRegion (IROU, SystemIO, Local3, 4)
- Field (IROU, AnyAcc, NoLock, Preserve) {
- GROU, 32,
- }
-
- // GPIO_ROUTE[GPIO] = 0 (SCI)
- Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU)
-
- //
- // Set GPnCONFIG to GPIO|INPUT|INVERT
- //
-
- // Local3 = GPIOBASE + GPnCONFIG0(GPIO)
- Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3)
-
- // GPnCONFIG(GPIO)
- OperationRegion (GPNC, SystemIO, Local3, 8)
- Field (GPNC, AnyAcc, NoLock, Preserve) {
- GMOD, 1, // MODE: 0=NATIVE 1=GPIO
- , 1,
- GIOS, 1, // IO_SEL: 0=OUTPUT 1=INPUT
- GINV, 1, // INVERT: 0=NORMAL 1=INVERT
- GLES, 1, // LxEB: 0=EDGE 1=LEVEL
- , 24,
- ILVL, 1, // INPUT: 0=LOW 1=HIGH
- OLVL, 1, // OUTPUT: 0=LOW 1=HIGH
- GPWP, 2, // PULLUP: 00=NONE 01=DOWN 10=UP 11=INVALID
- ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE
- }
-
- Store (0x1, GMOD) // GPIO
- Store (0x1, GIOS) // INPUT
- Store (0x1, GINV) // INVERT
- }
}
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index 61d80bd..625acdb 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -476,4 +476,9 @@
#define PAD_TERM_667_PU 13
#define PAD_TERM_NATIVE 15
+#define MISCCFG_OFFSET 0x10
+#define GPIO_DRIVER_IRQ_ROUTE_MASK 8
+#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0
+#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8
+
#endif /* _SOC_GPIO_DEFS_H_ */
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index c56b8e4..916719d 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -57,6 +57,8 @@
#define PCH_PWRM_BASE_ADDRESS 0xfe000000
#define PCH_PWRM_BASE_SIZE 0x10000
+#define GPIO_BASE_SIZE 0x10000
+
/*
* I/O port address space
*/
@@ -66,10 +68,6 @@
#define ACPI_BASE_ADDRESS 0x1800
#define ACPI_BASE_SIZE 0x100
-/* FIXME: not applicable as there is no I/O space for gpio access. */
-#define GPIO_BASE_ADDRESS 0x1400
-#define GPIO_BASE_SIZE 0x400
-
#define TCO_BASE_ADDDRESS 0x400
#define TCO_BASE_SIZE 0x20
diff --git a/src/soc/intel/skylake/include/soc/irq.h b/src/soc/intel/skylake/include/soc/irq.h
index 7f3fd65..430a13c 100644
--- a/src/soc/intel/skylake/include/soc/irq.h
+++ b/src/soc/intel/skylake/include/soc/irq.h
@@ -17,6 +17,8 @@
#ifndef _SOC_IRQ_H_
#define _SOC_IRQ_H_
+#define GPIO_IRQ14 14
+#define GPIO_IRQ15 15
#define LPSS_I2C0_IRQ 16
#define LPSS_I2C1_IRQ 17
#define LPSS_I2C2_IRQ 18
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