[coreboot-gerrit] New patch to review for coreboot: skylake: remove ec_smi_gpio and alt_gp_smi_en
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Wed Aug 12 17:52:24 CEST 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11204
-gerrit
commit 742cede3a3f9bd91ae1ad20923bb6af674bde409
Author: Aaron Durbin <adurbin at chromium.org>
Date: Fri Aug 7 22:57:42 2015 -0500
skylake: remove ec_smi_gpio and alt_gp_smi_en
The ec_smi_gpio and alt_gp_smi_en devicetree options are
goign to be removed. The plan for skylake is to set the
settings by the mainboard through either gpio pad
configuration or through helper functions.
Moreover, these values only allow *1* SMI GPIO configuration
in that the following has to be true:
alt_gp_smi_en = 1 << (ec_smi_gpio % 24)
If not, then another gpio(s) from the same group has the
SMI_EN bit set for it.
Lastly, remove all the subsequent dependencies as they are
no longer used: enable_alt_smi() and gpio_enable_group().
BUG=chrome-os-partner:43778
BRANCH=None
TEST=None
Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291931
Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/intel/kunimitsu/devicetree.cb | 5 +----
src/mainboard/intel/sklrvp/devicetree.cb | 4 +---
src/soc/intel/skylake/chip.h | 4 ----
src/soc/intel/skylake/gpio.c | 18 ------------------
src/soc/intel/skylake/include/soc/gpio.h | 3 ---
src/soc/intel/skylake/include/soc/pm.h | 1 -
src/soc/intel/skylake/pmc.c | 3 ---
src/soc/intel/skylake/pmutil.c | 8 --------
8 files changed, 2 insertions(+), 44 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 7f1b35f..6f03bbf 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -28,11 +28,8 @@ chip soc/intel/skylake
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
- # EC_SMI
- register "ec_smi_gpio" = "34"
- register "alt_gp_smi_en" = "0x0400"
+ # GPE configuration
register "gpe0_en_1" = "0x00000000"
-
# EC_SCI is GPIO36
register "gpe0_en_2" = "0x00000010"
register "gpe0_en_3" = "0x00000000"
diff --git a/src/mainboard/intel/sklrvp/devicetree.cb b/src/mainboard/intel/sklrvp/devicetree.cb
index 128c222..cfa51a8 100644
--- a/src/mainboard/intel/sklrvp/devicetree.cb
+++ b/src/mainboard/intel/sklrvp/devicetree.cb
@@ -49,9 +49,7 @@ chip soc/intel/skylake
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
- # EC_SMI
- register "ec_smi_gpio" = "34"
- register "alt_gp_smi_en" = "0x0400"
+ # GPE configuration
register "gpe0_en_1" = "0x00000000"
# EC_SCI is GPIO36
register "gpe0_en_2" = "0x00000010"
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 873342a..9fe1ed2 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -54,10 +54,6 @@ struct soc_intel_skylake_config {
uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
- /* GPIO SMI configuration */
- uint32_t ec_smi_gpio;
- uint32_t alt_gp_smi_en;
-
/* Generic IO decode ranges */
uint32_t gen1_dec;
uint32_t gen2_dec;
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 1863887..afd838f 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -371,21 +371,3 @@ void gpio_enable_all_smi(void)
0xFFFFFFFF);
}
}
-
-void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask)
-{
- u32 gpioindex = 0;
- u32 smien = 0;
-
- if (gpio_num > MAX_GPIO_NUMBER)
- return;
-
- gpioindex = (gpio_num / MAX_GPIO_PIN_PER_GROUP);
-
- pcr_read32(gpio_group_info[gpioindex].community,
- gpio_group_info[gpioindex].smienoffset, &smien);
- smien |= mask;
- /* Set all GPI SMI Enable bits by writing '1' */
- pcr_write32(gpio_group_info[gpioindex].community,
- gpio_group_info[gpioindex].smienoffset, smien);
-}
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index 321f04c..1c462a7 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -40,9 +40,6 @@ void gpio_get_smi_status(u32 status[GPIO_COMMUNITY_MAX]);
/* Enable GPIO SMI */
void gpio_enable_all_smi(void);
-/* Enable GPIO individual Group SMI */
-void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask);
-
/*
* Set the GPIO groups for the GPE blocks. The gpe0_route is interpreted
* as the packed configuration for GPE0_DW[2:0]:
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 9409ba2..c0a165e 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -176,7 +176,6 @@ void disable_smi(uint32_t mask);
/* ALT_GP_SMI */
uint32_t clear_alt_smi_status(void);
-void enable_alt_smi(int gpionum, u32 mask);
void reset_alt_smi_status(void);
/* TCO */
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index b6c35eb..2704956 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -227,9 +227,6 @@ static void pch_power_options(void)
/* Set up GPE configuration. */
pmc_gpe_init(config);
-
- /* SMI setup based on device tree configuration */
- enable_alt_smi(config->ec_smi_gpio, config->alt_gp_smi_en);
}
static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index e5d4a2e..8e54db4 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -258,14 +258,6 @@ u32 clear_alt_smi_status(void)
return print_alt_smi_status();
}
-/* Enable GPIO SMI events */
-void enable_alt_smi(int gpionum, u32 mask)
-{
- /*Set GPIO EN Status*/
- gpio_enable_groupsmi(gpionum, mask);
-}
-
-
/*
* TCO
*/
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