[coreboot-gerrit] Patch merged into coreboot/master: skylake: set DISB in GEN_PMCON_A register properly

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 85654a66504f2c87f129d3c414995be4b6cdc09f
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Aug 4 14:04:47 2015 -0500

    skylake: set DISB in GEN_PMCON_A register properly
    
    DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM
    training is complete. However, as a 8-bit write was
    being performed the bit was never being set.
    
    BUG=chrome-os-partner:43516
    BRANCH=None
    TEST=Built and booted to kernel. Rebooted. Noted full memory
         training was not being peformed.
    
    Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/290337
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    
    Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11183
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11183 for details.

-gerrit