[coreboot-gerrit] Patch set updated for coreboot: glados: make EC_SCI_L work
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Fri Aug 14 15:23:15 CEST 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11210
-gerrit
commit a94359ced76201886d570384d3a202cf2221f190
Author: Aaron Durbin <adurbin at chromium.org>
Date: Sun Aug 9 14:45:02 2015 -0500
glados: make EC_SCI_L work
In order for the EC_SCI_L to work the GPE0 route needs
to be set along w/ the GPE event for the EC. As the GPE0
route is dynamic the EC_SCI_GPI needs to be set along
with the route so everything lines up. In this case, the
GPE0 route is set to the defaults such that GPP_C, GPP_D,
and GPP_E are routed to GPE0 block 0, 1, and 2, respectively.
This works out for glados because the EC_SCI_L is connected
to GPP_E16.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados. The 'acpi' interrupt in /proc/interrupts
is incrementing as well as /sys/firmware/acpi/interrupts/gpe50.
Original-Change-Id: I71fc4bec124f3ac87453a099412154e67aba6280
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/292011
Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Change-Id: Idbb6d29364655537abc9ae6f012b3abb38edf138
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/glados/devicetree.cb | 8 ++++++++
src/mainboard/google/glados/ec.h | 6 ++++--
src/mainboard/google/glados/gpio.h | 2 +-
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 2e1cae7..9bb065d 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -49,6 +49,14 @@ chip soc/intel/skylake
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
# Embedded Controller host command window
register "gen1_dec" = "0x00fc0801"
diff --git a/src/mainboard/google/glados/ec.h b/src/mainboard/google/glados/ec.h
index f42e4c7..d43b57c 100644
--- a/src/mainboard/google/glados/ec.h
+++ b/src/mainboard/google/glados/ec.h
@@ -24,8 +24,10 @@
#include <ec/google/chromeec/ec_commands.h>
#include <soc/gpio.h>
-/* GPP_E16 is EC_SCI_L */
-#define EC_SCI_GPI 16 /* TODO: Update this */
+/* GPP_E16 is EC_SCI_L, however the EC_SCI_GPI needs to be a bit
+ * number relative to the GPE0 block. GPP_E is routed as the dword 2
+ * in the GPE0 block. Therefore, 16 + 2 * 32 = 80. */
+#define EC_SCI_GPI 80
#define EC_SMI_GPI GPP_E15
#define MAINBOARD_EC_SCI_EVENTS \
diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h
index ebbee20..c7cd5ae 100644
--- a/src/mainboard/google/glados/gpio.h
+++ b/src/mainboard/google/glados/gpio.h
@@ -135,7 +135,7 @@ static const struct pad_config gpio_table[] = {
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */
-/* DDPE_HPD3 */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
+/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
/* DDPB_CTRLCLK */ /* GPP_E18 */
/* DDPB_CTRLDATA */ /* GPP_E19 */
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