[coreboot-gerrit] Patch merged into coreboot/master: Skylake: Add ASL code to enable GPIO controller

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit ee9662824d41765a90d0dde6870d8f13737bc3a6
Author: Archana Patni <archana.patni at intel.com>
Date:   Sat Jul 4 00:56:32 2015 +0530

    Skylake: Add ASL code to enable GPIO controller
    
    This patch enables GPIO controller for skylake. It adds
    community base addresses and offset for Community0, Community1,
    and Community3. Community2 is not exposed in BIOS or enabled
    in the kernel driver.
    
    Also, clean up the carry over GWAK implementation from BDW.
    
    BRANCH=None
    BUG=chrome-os-partner:42393
    TEST=cat /sys/kernel/debug/gpio should list of GPIOs
    TEST=export a GPIO pin using /sys/class/gpio/export
    
    Original-Change-Id: I891c40589d3dbd796cf593626472c7b5674a1ae0
    Original-Signed-off-by: Archana Patni <archana.patni at intel.com>
    Original-Signed-off-by: Subramony Sesha <subramony.sesha at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/291230
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Original-Commit-Queue: Aaron Durbin <adurbin at chromium.org>
    
    Change-Id: I7481ce682ccae872fddf81b3188c3415d5d3f7d9
    Signed-off-by: Archana Patni <archana.patni at intel.com>
    Signed-off-by: Subramony Sesha <subramony.sesha at intel.com>
    Reviewed-on: http://review.coreboot.org/11191
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11191 for details.

-gerrit