[coreboot-gerrit] New patch to review for coreboot: skylake: make PAD_CFG_GPI default to GPIO ownership

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11283

-gerrit

commit e1a2fe783d30b3416d65458585ebba7b4bb0c68c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Aug 17 16:27:09 2015 -0500

    skylake: make PAD_CFG_GPI default to GPIO ownership
    
    The prior implementation of PAD_CFG_GPI kept the pad
    ownership as ACPI. The gpio driver in the kernel then
    wouldn't allow one to export those GPIOs through sysfs
    in /sys/class/gpio. Fix this by setting the ownership
    to GPIO.
    
    BUG=chrome-os-partner:44147
    BRANCH=None
    TEST=Built and boot glados. PCH_WP gpio is properly exported
         by crossystem.
    
    Original-Change-Id: I9fc7ab141a3fd74e0ff8b3ff5009b007b8a0d69b
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/294081
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    
    Change-Id: Ifbb61c5d64bb6a04f140685c70f4681e2babecef
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/include/soc/gpio.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index 488a2b5..4871c8c 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -121,8 +121,9 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
 
 /* General purpose input with no special IRQ routing. */
 #define PAD_CFG_GPI(pad_, term_, rst_) \
-	_PAD_CFG(pad_, term_, \
-	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES))
+	_PAD_CFG_ATTRS(pad_, term_, \
+	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\
+	PAD_FIELD(HOSTSW, GPIO))
 
 /* General purpose input passed through to IOxAPIC. Assume APIC logic can
  * handle polarity/edge/level constraints. */