[coreboot-gerrit] New patch to review for coreboot: kontron/ktqm77: Tag all four USB3 ports switchable and SS capable

[Nico Huber (nico.h@gmx.de)]

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11287

-gerrit

commit a1600a7699ab3407609b0ba1471cda8137707651
Author: Nico Huber <nico.huber at secunet.com>
Date:   Wed Aug 19 15:46:13 2015 +0200

    kontron/ktqm77: Tag all four USB3 ports switchable and SS capable
    
    With the introduction of these options in
    
    commit b26156ec65f1622f97d4439b3977c7880f234054
    Author: Vladimir Serbinenko <phcoder at gmail.com>
    Date:   Sat Jan 31 17:45:50 2015 +0100
    
        bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.
    
    the default regressed to disable these capabilities. Maybe other boards
    regressed, too. I didn't check.
    
    Change-Id: I220896e656d00145618e61d55b74904517c7d855
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/mainboard/kontron/ktqm77/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb
index b916b0b..ff5d012 100644
--- a/src/mainboard/kontron/ktqm77/devicetree.cb
+++ b/src/mainboard/kontron/ktqm77/devicetree.cb
@@ -44,6 +44,9 @@ chip northbridge/intel/sandybridge
 			register "c2_latency" = "101"  # c2 not supported
 			register "p_cnt_throttling_supported" = "1"
 
+			register "xhci_switchable_ports"	= "0x0f"
+			register "superspeed_capable_ports"	= "0x0f"
+
 			device pci 14.0 on end # USB 3.0 Controller
 			device pci 16.0 on end # Management Engine Interface 1
 			device pci 16.1 off end # Management Engine Interface 2