[coreboot-gerrit] New patch to review for coreboot: t210: Move page tables to end of TZDRAM

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11383

-gerrit

commit aa2972dfe1fd5f6cbb5aef2bddce405563249a3a
Author: Furquan Shaikh <furquan at google.com>
Date:   Wed Aug 5 17:03:34 2015 -0700

    t210: Move page tables to end of TZDRAM
    
    BL31 makes an assumption that TZDRAM always starts at its base. This
    was not true in our case since coreboot page tables were located
    towards the start of TZDRAM. Instead move page tables to the end, thus
    satisfying the assumption that BL31 base is the base of TZDRAM as
    well.
    
    BUG=chrome-os-partner:42989
    BRANCH=None
    TEST=Compiles successfully and boots to kernel prompt
    
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: aabed336da6e9aea426650c5ca5977ccfc83a21b
    Original-Change-Id: Ic4d155525dbb4baab95c971f77848e47d5d54dba
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/291020
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    Original-Trybot-Ready: Furquan Shaikh <furquan at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-(cherry picked from commit a57127f1655ef311b82c41ce33ffc71db5f9db35)
    Original-Reviewed-on: https://chromium-review.googlesource.com/290987
    
    Change-Id: Ie7166fd0301b46eb32f44107f7f782c6d79a278c
---
 src/soc/nvidia/tegra210/Makefile.inc     |  9 +++-----
 src/soc/nvidia/tegra210/mmu_operations.c | 35 +++++++++++++++++++++++++++++---
 2 files changed, 35 insertions(+), 9 deletions(-)

diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc
index 0593f06..fb38d38 100644
--- a/src/soc/nvidia/tegra210/Makefile.inc
+++ b/src/soc/nvidia/tegra210/Makefile.inc
@@ -161,14 +161,11 @@ endif
 
 # BL31 component is placed towards the end of 32-bit address space. This assumes
 # that TrustZone memory is placed at the end of 32-bit address space. Within the
-# TZ memory, we place TTB at the beginning and then remaining space can be used
-# up by BL31 and secure OS. Calculate TZDRAM_BASE i.e. base of BL31 component
-# by:
+# TZ memory, we place BL31 and BL32(if available) towards the beginning and TTB
+# towards the end. Calculate TZDRAM_BASE i.e. base of BL31 component by:
 #   0x1000 = end of 32-bit address space in MiB
 #   0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) = start of TZ memory in MiB
-#   0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB)
-#             = skip TTB buffer and get base address of BL31
-BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB)) << 20))
+BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) << 20))
 BL31_MAKEARGS += PLAT=tegra TARGET_SOC=t210
 
 # MTC fw
diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c
index dd7437c..5578933 100644
--- a/src/soc/nvidia/tegra210/mmu_operations.c
+++ b/src/soc/nvidia/tegra210/mmu_operations.c
@@ -18,6 +18,7 @@
  */
 
 #include <arch/mmu.h>
+#include <assert.h>
 #include <memrange.h>
 #include <soc/addressmap.h>
 #include <soc/mmu_operations.h>
@@ -69,15 +70,43 @@ void tegra210_mmu_init(void)
 {
 	uintptr_t tz_base_mib;
 	size_t tz_size_mib;
+	uintptr_t ttb_base_mib;
 	size_t ttb_size_mib;
 	struct memranges *map = &t210_mmap_ranges;
 
 	tegra210_memrange_init(map);
 	mainboard_add_memory_ranges(map);
-	/* Place page tables at the base of the trust zone region. */
+	/*
+	 * Place page tables at the end of the trust zone region.
+	 * TZDRAM layout is as follows:
+	 *
+	 * +--------------------------+ <----+DRAM_END
+	 * |                          |
+	 * |                          |
+	 * |                          |
+	 * +--------------------------+ <----+0x100000000
+	 * |                          |
+	 * |   coreboot page tables   |
+	 * +--------------------------+
+	 * |                          |
+	 * |        BL32              |
+	 * +--------------------------+
+	 * |                          |
+	 * |        BL31              |
+	 * +--------------------------+ <----+TZDRAM_BASE
+	 * |                          |
+	 * |                          |
+	 * |                          |
+	 * |                          |
+	 * +--------------------------+ <----+DRAM_BASE
+	 *
+	 */
 	carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
-	tz_base_mib *= MiB;
+
+	assert(tz_size_mib > CONFIG_TTB_SIZE_MB);
+	ttb_base_mib = (tz_base_mib + tz_size_mib - CONFIG_TTB_SIZE_MB) * MiB;
+
 	ttb_size_mib = CONFIG_TTB_SIZE_MB * MiB;
-	mmu_init(map, (void *)tz_base_mib, ttb_size_mib);
+	mmu_init(map, (void *)ttb_base_mib, ttb_size_mib);
 	mmu_enable();
 }