[coreboot-gerrit] New patch to review for coreboot: rockchip: rk3288: multiple NPLL rate in pll_para_config

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11393

-gerrit

commit 6064ce9bedfa40049ca08b0d3eaafb6147ec69b8
Author: Yakir Yang <ykk at rock-chips.com>
Date:   Mon Jul 27 08:50:36 2015 -0500

    rockchip: rk3288: multiple NPLL rate in pll_para_config
    
    Due to HDMI need to set dclk_rate to 27Mhz, and we can't
    caclu a suitable config paramters for this rate, so we
    need to multiple rate unless the vco larger then VCO_MAX.
    
    When NPLL rate multiple to 54MHz, pll_para_config could
    caclu a right paramters, and I have verify the clock jitter
    is okay to HDMI output.
    
    Jitter Reports:
    Dclk Rate      NPLL Rate      nr/no/nf      jitter      Margin
    27MHz          54MHz          2/10/45       449.0ps     +51.0%
    
    BRANCH=None
    BUG=chrome-os-partner:42946
    TEST=Mickey board, show right recovery picture on TV,
         and 480p clock jitter test passed
    
    Change-Id: Iaa0a6622e63d88918ed465900e630bdf16fde706
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: 59f1552026889f61167cfeaec3def668ba709c10
    Original-Signed-off-by: Yakir Yang <ykk at rock-chips.com>
    Original-Change-Id: Iab274b41f163d2d61332df13e5091f0b605cb65c
    Original-Reviewed-on: https://chromium-review.googlesource.com/288416
    Original-Commit-Queue: David Hendricks <dhendrix at chromium.org>
    Original-Tested-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/290331
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
 src/soc/rockchip/rk3288/clock.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index 878c194..e4d2e3e 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -498,7 +498,7 @@ void rkclk_configure_tsadc(unsigned int hz)
 		RK_CLRSETBITS(0x3f << 0, (div - 1) << 0));
 }
 
-static int pll_para_config(u32 freq_hz, struct pll_div *div)
+static int pll_para_config(u32 freq_hz, struct pll_div *div, u32 *ext_div)
 {
 	u32 ref_khz = OSC_HZ / KHz, nr, nf = 0;
 	u32 fref_khz;
@@ -512,17 +512,27 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
 		printk(BIOS_ERR, "%s: the frequency can not be 0 Hz\n", __func__);
 		return -1;
 	}
+
 	no = div_round_up(VCO_MIN_KHZ, freq_khz);
+	if (ext_div) {
+		*ext_div = div_round_up(no, max_no);
+		no = div_round_up(no, *ext_div);
+	}
 
 	/* only even divisors (and 1) are supported */
 	if (no > 1)
 		no = div_round_up(no, 2) * 2;
+
 	vco_khz = freq_khz * no;
+	if (ext_div)
+		vco_khz *= *ext_div;
+
 	if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 		printk(BIOS_ERR, "%s: Cannot find out a supported VCO"
 		" for Frequency (%uHz).\n", __func__, freq_hz);
 		return -1;
 	}
+
 	div->no = no;
 
 	best_diff_khz = vco_khz;
@@ -608,8 +618,9 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz)
 int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
 {
 	struct pll_div npll_config = {0};
+	u32 lcdc_div;
 
-	if (pll_para_config(dclk_hz, &npll_config))
+	if (pll_para_config(dclk_hz, &npll_config, &lcdc_div))
 		return -1;
 
 	/* npll enter slow-mode */
@@ -633,12 +644,14 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
 	switch (vop_id) {
 	case 0:
 		write32(&cru_ptr->cru_clksel_con[27],
-			RK_CLRSETBITS(0xff << 8 | 3 << 0, 0 << 8 | 2 << 0));
+			RK_CLRSETBITS(0xff << 8 | 3 << 0,
+				      (lcdc_div - 1) << 8 | 2 << 0));
 		break;
 
 	case 1:
 		write32(&cru_ptr->cru_clksel_con[29],
-			RK_CLRSETBITS(0xff << 8 | 3 << 6, 0 << 8 | 2 << 6));
+			RK_CLRSETBITS(0xff << 8 | 3 << 6,
+				      (lcdc_div - 1) << 8 | 2 << 6));
 		break;
 	}
 	return 0;