[coreboot-gerrit] Patch set updated for coreboot: edid: Use edid_mode struct to reduce redundancy
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Aug 27 17:28:22 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11388
-gerrit
commit d4e3232ca8d0d6b7b21b6ac48292ef5c3e151be5
Author: David Hendricks <dhendrix at chromium.org>
Date: Thu Jul 30 18:49:48 2015 -0700
edid: Use edid_mode struct to reduce redundancy
This replaces various timing mode parameters parameters with
an edid_mode struct within the edid struct.
BUG=none
BRANCH=firmware-veyron
TEST=built and booted on Mickey, saw display come up, also
compiled for link,falco,peppy,rambi,nyan_big,rush,smaug
[pg: extended to also cover peach_pit, daisy and lenovo/t530]
Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9
Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6
Original-Signed-off-by: David Hendricks <dhendrix at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289964
Original-Reviewed-by: Yakir Yang <ykk at rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
src/drivers/intel/gma/display.c | 27 ++++++------
src/include/edid.h | 39 +++++++++++------
src/lib/edid.c | 49 +++++++++++-----------
src/mainboard/google/daisy/mainboard.c | 4 +-
src/mainboard/google/falco/gma.c | 4 +-
src/mainboard/google/peach_pit/mainboard.c | 4 +-
src/mainboard/google/peppy/gma.c | 12 +++---
.../intel/sandybridge/gma_ivybridge_lvds.c | 28 ++++++-------
src/soc/nvidia/tegra124/dp.c | 18 ++++----
src/soc/nvidia/tegra132/dp.c | 18 ++++----
src/soc/nvidia/tegra210/dp.c | 18 ++++----
src/soc/rockchip/rk3288/display.c | 8 ++--
src/soc/rockchip/rk3288/hdmi.c | 36 ++++++++--------
src/soc/rockchip/rk3288/vop.c | 32 +++++++-------
14 files changed, 156 insertions(+), 141 deletions(-)
diff --git a/src/drivers/intel/gma/display.c b/src/drivers/intel/gma/display.c
index 5c8e886..afcec91 100644
--- a/src/drivers/intel/gma/display.c
+++ b/src/drivers/intel/gma/display.c
@@ -38,6 +38,7 @@
void compute_display_params(struct intel_dp *dp)
{
struct edid *edid = &(dp->edid);
+ struct edid_mode *mode = &edid->mode;
/* step 1: get the constants in the dp struct set up. */
dp->lane_count = dp->dpcd[DP_MAX_LANE_COUNT]&DP_LANE_COUNT_MASK;
@@ -51,22 +52,22 @@ void compute_display_params(struct intel_dp *dp)
dp->stride = edid->bytes_per_line;
- dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
+ dp->htotal = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16);
- dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
+ dp->hblank = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16);
- dp->hsync = (edid->ha + edid->hso - 1) |
- ((edid->ha + edid->hso + edid->hspw - 1) << 16);
+ dp->hsync = (mode->ha + mode->hso - 1) |
+ ((mode->ha + mode->hso + mode->hspw - 1) << 16);
- dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
+ dp->vtotal = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16);
- dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
+ dp->vblank = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16);
- dp->vsync = (edid->va + edid->vso - 1) |
- ((edid->va + edid->vso + edid->vspw - 1) << 16);
+ dp->vsync = (mode->va + mode->vso - 1) |
+ ((mode->va + mode->vso + mode->vspw - 1) << 16);
/* PIPEASRC is wid-1 x ht-1 */
- dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1);
+ dp->pipesrc = (mode->ha-1)<<16 | (mode->va-1);
dp->pfa_pos = 0;
@@ -75,7 +76,7 @@ void compute_display_params(struct intel_dp *dp)
if (dp->gen == 6)
dp->pfa_ctl |= PF_PIPE_SEL_IVB(dp->pipe);
- dp->pfa_sz = (edid->ha << 16) | (edid->va);
+ dp->pfa_sz = (mode->ha << 16) | (mode->va);
/* step 3. Call the linux code we pulled in. */
dp->flags = intel_ddi_calc_transcoder_flags(edid->panel_bits_per_pixel,
@@ -84,15 +85,15 @@ void compute_display_params(struct intel_dp *dp)
dp->type,
dp->lane_count,
dp->pfa_sz,
- dp->edid.phsync == '+'?1:0,
- dp->edid.pvsync == '+'?1:0);
+ mode->phsync == '+'?1:0,
+ mode->pvsync == '+'?1:0);
dp->transcoder = intel_ddi_get_transcoder(dp->port,
dp->pipe);
intel_dp_compute_m_n(edid->panel_bits_per_pixel,
dp->lane_count,
- dp->edid.pixel_clock,
+ dp->edid.mode.pixel_clock,
dp->edid.link_clock,
&dp->m_n);
diff --git a/src/include/edid.h b/src/include/edid.h
index 1422c1e..3de4dbc 100644
--- a/src/include/edid.h
+++ b/src/include/edid.h
@@ -20,6 +20,31 @@
#ifndef EDID_H
#define EDID_H
+enum edid_modes {
+ EDID_MODE_AUTO = 0,
+ EDID_MODE_640x480_60Hz,
+};
+
+struct edid_mode {
+ const char *name;
+ unsigned int pixel_clock;
+ unsigned int refresh;
+ unsigned int ha;
+ unsigned int hbl;
+ unsigned int hso;
+ unsigned int hspw;
+ unsigned int hborder;
+ unsigned int va;
+ unsigned int vbl;
+ unsigned int vso;
+ unsigned int vspw;
+ unsigned int vborder;
+ unsigned char phsync;
+ unsigned char pvsync;
+ unsigned int x_mm;
+ unsigned int y_mm;
+};
+
/* structure for communicating EDID information from a raw EDID block to
* higher level functions.
* The size of the data types is not critical, so we leave them as
@@ -49,20 +74,8 @@ struct edid {
*/
unsigned int panel_bits_per_pixel;
/* used to compute timing for graphics chips. */
- unsigned char phsync;
- unsigned char pvsync;
- unsigned int pixel_clock;
+ struct edid_mode mode;
unsigned int link_clock;
- unsigned int ha;
- unsigned int hbl;
- unsigned int hso;
- unsigned int hspw;
- unsigned int hborder;
- unsigned int va;
- unsigned int vbl;
- unsigned int vso;
- unsigned int vspw;
- unsigned int vborder;
/* 3 variables needed for coreboot framebuffer.
* In most cases, they are the same as the ha
* and va variables, but not always, as in the
diff --git a/src/lib/edid.c b/src/lib/edid.c
index e08535d..22f3f0e 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -445,19 +445,19 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension,
if (! c->did_detailed_timing){
/* Edid contains pixel clock in terms of 10KHz */
- out->pixel_clock = (x[0] + (x[1] << 8)) * 10;
+ out->mode.pixel_clock = (x[0] + (x[1] << 8)) * 10;
extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4));
extra_info.y_mm = (x[13] + ((x[14] & 0x0F) << 8));
- out->ha = (x[2] + ((x[4] & 0xF0) << 4));
- out->hbl = (x[3] + ((x[4] & 0x0F) << 8));
- out->hso = (x[8] + ((x[11] & 0xC0) << 2));
- out->hspw = (x[9] + ((x[11] & 0x30) << 4));
- out->hborder = x[15];
- out->va = (x[5] + ((x[7] & 0xF0) << 4));
- out->vbl = (x[6] + ((x[7] & 0x0F) << 8));
- out->vso = ((x[10] >> 4) + ((x[11] & 0x0C) << 2));
- out->vspw = ((x[10] & 0x0F) + ((x[11] & 0x03) << 4));
- out->vborder = x[16];
+ out->mode.ha = (x[2] + ((x[4] & 0xF0) << 4));
+ out->mode.hbl = (x[3] + ((x[4] & 0x0F) << 8));
+ out->mode.hso = (x[8] + ((x[11] & 0xC0) << 2));
+ out->mode.hspw = (x[9] + ((x[11] & 0x30) << 4));
+ out->mode.hborder = x[15];
+ out->mode.va = (x[5] + ((x[7] & 0xF0) << 4));
+ out->mode.vbl = (x[6] + ((x[7] & 0x0F) << 8));
+ out->mode.vso = ((x[10] >> 4) + ((x[11] & 0x0C) << 2));
+ out->mode.vspw = ((x[10] & 0x0F) + ((x[11] & 0x03) << 4));
+ out->mode.vborder = x[16];
/* set up some reasonable defaults for payloads.
* We observe that most modern chipsets we work with
* tend to support rgb888 without regard to the
@@ -475,11 +475,11 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension,
*/
out->framebuffer_bits_per_pixel = 32;
- out->x_resolution = ALIGN(out->ha *
+ out->x_resolution = ALIGN(out->mode.ha *
((out->framebuffer_bits_per_pixel + 7) / 8),
64) / (out->framebuffer_bits_per_pixel/8);
- out->y_resolution = out->va;
- out->bytes_per_line = ALIGN(out->ha *
+ out->y_resolution = out->mode.va;
+ out->bytes_per_line = ALIGN(out->mode.ha *
((out->framebuffer_bits_per_pixel + 7)/8),
64);
printk(BIOS_SPEW, "Did detailed timing\n");
@@ -499,8 +499,8 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension,
extra_info.syncmethod = "";
break;
}
- out->pvsync = (x[17] & (1 << 2)) ? '+' : '-';
- out->phsync = (x[17] & (1 << 1)) ? '+' : '-';
+ out->mode.pvsync = (x[17] & (1 << 2)) ? '+' : '-';
+ out->mode.phsync = (x[17] & (1 << 1)) ? '+' : '-';
switch (x[17] & 0x61) {
case 0x20:
extra_info.stereo = "field sequential L/R";
@@ -529,17 +529,18 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension,
" %04x %04x %04x %04x hborder %x\n"
" %04x %04x %04x %04x vborder %x\n"
" %chsync %cvsync%s%s %s\n",
- out->pixel_clock,
+ out->mode.pixel_clock,
extra_info.x_mm,
extra_info.y_mm,
- out->ha, out->ha + out->hso, out->ha + out->hso + out->hspw,
- out->ha + out->hbl, out->hborder,
- out->va, out->va + out->vso, out->va + out->vso + out->vspw,
- out->va + out->vbl, out->vborder,
- out->phsync, out->pvsync,
+ out->mode.ha, out->mode.ha + out->mode.hso,
+ out->mode.ha + out->mode.hso + out->mode.hspw,
+ out->mode.ha + out->mode.hbl, out->mode.hborder,
+ out->mode.va, out->mode.va + out->mode.vso,
+ out->mode.va + out->mode.vso + out->mode.vspw,
+ out->mode.va + out->mode.vbl, out->mode.vborder,
+ out->mode.phsync, out->mode.pvsync,
extra_info.syncmethod, x[17] & 0x80 ?" interlaced" : "",
- extra_info.stereo
- );
+ extra_info.stereo);
return 1;
}
diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c
index b4b9e50..9bbd88e 100644
--- a/src/mainboard/google/daisy/mainboard.c
+++ b/src/mainboard/google/daisy/mainboard.c
@@ -48,8 +48,8 @@
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
static struct edid edid = {
- .ha = 1366,
- .va = 768,
+ .mode.ha = 1366,
+ .mode.va = 768,
.framebuffer_bits_per_pixel = 16,
.x_resolution = 1366,
.y_resolution = 768,
diff --git a/src/mainboard/google/falco/gma.c b/src/mainboard/google/falco/gma.c
index 68f1e45..6c936d7 100644
--- a/src/mainboard/google/falco/gma.c
+++ b/src/mainboard/google/falco/gma.c
@@ -234,8 +234,8 @@ int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
palette();
- pixels = dp->edid.ha * (dp->edid.va-4) * 4;
- printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
+ pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4;
+ printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va);
test_gfx(dp);
diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c
index b5d2410..37f5986 100644
--- a/src/mainboard/google/peach_pit/mainboard.c
+++ b/src/mainboard/google/peach_pit/mainboard.c
@@ -47,8 +47,8 @@
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
static struct edid edid = {
- .ha = 1366,
- .va = 768,
+ .mode.ha = 1366,
+ .mode.va = 768,
.framebuffer_bits_per_pixel = 16,
.x_resolution = 1366,
.y_resolution = 768,
diff --git a/src/mainboard/google/peppy/gma.c b/src/mainboard/google/peppy/gma.c
index 735ad65..4e2fc5f 100644
--- a/src/mainboard/google/peppy/gma.c
+++ b/src/mainboard/google/peppy/gma.c
@@ -151,12 +151,12 @@ static void test_gfx(struct intel_dp *dp)
are made right. Thus, to be used only for testing, not otherwise
*/
- for (i = 0; i < (dp->edid.va - 4); i++) {
+ for (i = 0; i < (dp->edid.mode.va - 4); i++) {
u32 *l;
int j;
u32 tcolor = 0x0ff;
- for (j = 0; j < (dp->edid.ha-4); j++) {
- if (j == (dp->edid.ha/2)) {
+ for (j = 0; j < (dp->edid.mode.ha-4); j++) {
+ if (j == (dp->edid.mode.ha/2)) {
tcolor = 0xff00;
}
l = (u32*)(dp->graphics + i * dp->stride + j * sizeof(tcolor));
@@ -246,7 +246,7 @@ int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
compute_display_params(dp);
printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",
- dp->edid.pixel_clock, dp->edid.link_clock);
+ dp->edid.mode.pixel_clock, dp->edid.link_clock);
intel_ddi_set_pipe_settings(dp);
@@ -254,8 +254,8 @@ int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
palette();
- pixels = dp->edid.ha * (dp->edid.va-4) * 4;
- printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
+ pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4;
+ printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va);
test_gfx(dp);
set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics);
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index a9648bb..65719d1 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -216,22 +216,22 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
u32 hactive = edid.x_resolution;
u32 vactive = edid.y_resolution;
- u32 right_border = edid.hborder;
- u32 bottom_border = edid.vborder;
- int hpolarity = (edid.phsync == '-');
- int vpolarity = (edid.pvsync == '-');
- u32 vsync = edid.vspw;
- u32 hsync = edid.hspw;
- u32 vblank = edid.vbl;
- u32 hblank = edid.hbl;
- u32 hfront_porch = edid.hso;
- u32 vfront_porch = edid.vso;
+ u32 right_border = edid.mode.hborder;
+ u32 bottom_border = edid.mode.vborder;
+ int hpolarity = (edid.mode.phsync == '-');
+ int vpolarity = (edid.mode.pvsync == '-');
+ u32 vsync = edid.mode.vspw;
+ u32 hsync = edid.mode.hspw;
+ u32 vblank = edid.mode.vbl;
+ u32 hblank = edid.mode.hbl;
+ u32 hfront_porch = edid.mode.hso;
+ u32 vfront_porch = edid.mode.vso;
u32 candp1, candn;
u32 best_delta = 0xffffffff;
- u32 target_frequency = info->lvds_dual_channel ? edid.pixel_clock
- : (2 * edid.pixel_clock);
+ u32 target_frequency = info->lvds_dual_channel ? edid.mode.pixel_clock
+ : (2 * edid.mode.pixel_clock);
u32 pixel_p1 = 1;
u32 pixel_n = 1;
u32 pixel_m1 = 1;
@@ -308,9 +308,9 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
u32 link_m1;
u32 link_n1 = 0x00080000;
- link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
+ link_m1 = ((uint64_t)link_n1 * edid.mode.pixel_clock) / link_frequency;
- data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
+ data_m1 = ((uint64_t)data_n1 * 18 * edid.mode.pixel_clock)
/ (link_frequency * 8 * (info->lvds_num_lanes ? : 1));
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c
index b3dab75..3a3bce8 100644
--- a/src/soc/nvidia/tegra124/dp.c
+++ b/src/soc/nvidia/tegra124/dp.c
@@ -1328,17 +1328,17 @@ static void tegra_dp_update_config(struct tegra_dc_dp_data *dp,
return;
}
- config->xres = edid.ha;
- config->yres = edid.va;
- config->pixel_clock = edid.pixel_clock * 1000;
+ config->xres = edid.mode.ha;
+ config->yres = edid.mode.va;
+ config->pixel_clock = edid.mode.pixel_clock * 1000;
- config->hfront_porch = edid.hso;
- config->hsync_width = edid.hspw;
- config->hback_porch = edid.hbl - edid.hso - edid.hspw;
+ config->hfront_porch = edid.mode.hso;
+ config->hsync_width = edid.mode.hspw;
+ config->hback_porch = edid.mode.hbl - edid.mode.hso - edid.mode.hspw;
- config->vfront_porch = edid.vso;
- config->vsync_width = edid.vspw;
- config->vback_porch = edid.vbl - edid.vso - edid.vspw;
+ config->vfront_porch = edid.mode.vso;
+ config->vsync_width = edid.mode.vspw;
+ config->vback_porch = edid.mode.vbl - edid.mode.vso - edid.mode.vspw;
/**
* Note edid->framebuffer_bits_per_pixel is currently hard-coded as 32,
diff --git a/src/soc/nvidia/tegra132/dp.c b/src/soc/nvidia/tegra132/dp.c
index 9714d44..17118e3 100644
--- a/src/soc/nvidia/tegra132/dp.c
+++ b/src/soc/nvidia/tegra132/dp.c
@@ -1367,18 +1367,18 @@ static void tegra_dp_update_config(struct tegra_dc_dp_data *dp,
return;
}
- config->xres = config->display_xres = edid.ha;
- config->yres = config->display_yres = edid.va;
+ config->xres = config->display_xres = edid.mode.ha;
+ config->yres = config->display_yres = edid.mode.va;
- config->pixel_clock = edid.pixel_clock * 1000;
+ config->pixel_clock = edid.mode.pixel_clock * 1000;
- config->hfront_porch = edid.hso;
- config->hsync_width = edid.hspw;
- config->hback_porch = edid.hbl - edid.hso - edid.hspw;
+ config->hfront_porch = edid.mode.hso;
+ config->hsync_width = edid.mode.hspw;
+ config->hback_porch = edid.mode.hbl - edid.mode.hso - edid.mode.hspw;
- config->vfront_porch = edid.vso;
- config->vsync_width = edid.vspw;
- config->vback_porch = edid.vbl - edid.vso - edid.vspw;
+ config->vfront_porch = edid.mode.vso;
+ config->vsync_width = edid.mode.vspw;
+ config->vback_porch = edid.mode.vbl - edid.mode.vso - edid.mode.vspw;
/**
* Note edid->framebuffer_bits_per_pixel is currently hard-coded as 32,
diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c
index ea6dbca..e047584 100644
--- a/src/soc/nvidia/tegra210/dp.c
+++ b/src/soc/nvidia/tegra210/dp.c
@@ -1367,18 +1367,18 @@ static void tegra_dp_update_config(struct tegra_dc_dp_data *dp,
return;
}
- config->xres = config->display_xres = edid.ha;
- config->yres = config->display_yres = edid.va;
+ config->xres = config->display_xres = edid.mode.ha;
+ config->yres = config->display_yres = edid.mode.va;
- config->pixel_clock = edid.pixel_clock * 1000;
+ config->pixel_clock = edid.mode.pixel_clock * 1000;
- config->hfront_porch = edid.hso;
- config->hsync_width = edid.hspw;
- config->hback_porch = edid.hbl - edid.hso - edid.hspw;
+ config->hfront_porch = edid.mode.hso;
+ config->hsync_width = edid.mode.hspw;
+ config->hback_porch = edid.mode.hbl - edid.mode.hso - edid.mode.hspw;
- config->vfront_porch = edid.vso;
- config->vsync_width = edid.vspw;
- config->vback_porch = edid.vbl - edid.vso - edid.vspw;
+ config->vfront_porch = edid.mode.vso;
+ config->vsync_width = edid.mode.vspw;
+ config->vback_porch = edid.mode.vbl - edid.mode.vso - edid.mode.vspw;
/**
* Note edid->framebuffer_bits_per_pixel is currently hard-coded as 32,
diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c
index d241e3e..02526a4 100644
--- a/src/soc/rockchip/rk3288/display.c
+++ b/src/soc/rockchip/rk3288/display.c
@@ -93,15 +93,15 @@ void rk_display_init(device_t dev, u32 lcdbase,
return;
}
- if (rkclk_configure_vop_dclk(conf->vop_id, edid.pixel_clock * KHz)) {
+ if (rkclk_configure_vop_dclk(conf->vop_id, edid.mode.pixel_clock * KHz)) {
printk(BIOS_WARNING, "config vop err\n");
return;
}
edid.framebuffer_bits_per_pixel = conf->framebuffer_bits_per_pixel;
- edid.bytes_per_line = edid.ha * conf->framebuffer_bits_per_pixel / 8;
- edid.x_resolution = edid.ha;
- edid.y_resolution = edid.va;
+ edid.bytes_per_line = edid.mode.ha * conf->framebuffer_bits_per_pixel / 8;
+ edid.x_resolution = edid.mode.ha;
+ edid.y_resolution = edid.mode.va;
rkvop_mode_set(conf->vop_id, &edid, detected_mode);
rkvop_enable(conf->vop_id, lcdbase, &edid);
diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c
index 582c834..a7a9c40 100644
--- a/src/soc/rockchip/rk3288/hdmi.c
+++ b/src/soc/rockchip/rk3288/hdmi.c
@@ -494,11 +494,11 @@ static void hdmi_av_composer(const struct edid *edid)
/* set up hdmi_fc_invidconf */
inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
- inv_val |= ((edid->pvsync == '+') ?
+ inv_val |= ((edid->mode.pvsync == '+') ?
HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
- inv_val |= ((edid->phsync == '+') ?
+ inv_val |= ((edid->mode.phsync == '+') ?
HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
@@ -517,33 +517,33 @@ static void hdmi_av_composer(const struct edid *edid)
write32(&hdmi_regs->fc_invidconf, inv_val);
/* set up horizontal active pixel width */
- write32(&hdmi_regs->fc_inhactv1, edid->ha >> 8);
- write32(&hdmi_regs->fc_inhactv0, edid->ha);
+ write32(&hdmi_regs->fc_inhactv1, edid->mode.ha >> 8);
+ write32(&hdmi_regs->fc_inhactv0, edid->mode.ha);
/* set up vertical active lines */
- write32(&hdmi_regs->fc_invactv1, edid->va >> 8);
- write32(&hdmi_regs->fc_invactv0, edid->va);
+ write32(&hdmi_regs->fc_invactv1, edid->mode.va >> 8);
+ write32(&hdmi_regs->fc_invactv0, edid->mode.va);
/* set up horizontal blanking pixel region width */
- write32(&hdmi_regs->fc_inhblank1, edid->hbl >> 8);
- write32(&hdmi_regs->fc_inhblank0, edid->hbl);
+ write32(&hdmi_regs->fc_inhblank1, edid->mode.hbl >> 8);
+ write32(&hdmi_regs->fc_inhblank0, edid->mode.hbl);
/* set up vertical blanking pixel region width */
- write32(&hdmi_regs->fc_invblank, edid->vbl);
+ write32(&hdmi_regs->fc_invblank, edid->mode.vbl);
/* set up hsync active edge delay width (in pixel clks) */
- write32(&hdmi_regs->fc_hsyncindelay1, edid->hso >> 8);
- write32(&hdmi_regs->fc_hsyncindelay0, edid->hso);
+ write32(&hdmi_regs->fc_hsyncindelay1, edid->mode.hso >> 8);
+ write32(&hdmi_regs->fc_hsyncindelay0, edid->mode.hso);
/* set up vsync active edge delay (in lines) */
- write32(&hdmi_regs->fc_vsyncindelay, edid->vso);
+ write32(&hdmi_regs->fc_vsyncindelay, edid->mode.vso);
/* set up hsync active pulse width (in pixel clks) */
- write32(&hdmi_regs->fc_hsyncinwidth1, edid->hspw >> 8);
- write32(&hdmi_regs->fc_hsyncinwidth0, edid->hspw);
+ write32(&hdmi_regs->fc_hsyncinwidth1, edid->mode.hspw >> 8);
+ write32(&hdmi_regs->fc_hsyncinwidth0, edid->mode.hspw);
/* set up vsync active edge delay (in lines) */
- write32(&hdmi_regs->fc_vsyncinwidth, edid->vspw);
+ write32(&hdmi_regs->fc_vsyncinwidth, edid->mode.vspw);
}
/* hdmi initialization step b.4 */
@@ -613,11 +613,11 @@ static int hdmi_setup(const struct edid *edid)
int ret;
hdmi_debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
- edid->pixel_clock, edid->ha, edid->va);
+ edid->mode.pixel_clock, edid->mode.ha, edid->mode.va);
hdmi_av_composer(edid);
- ret = hdmi_phy_init(edid->pixel_clock);
+ ret = hdmi_phy_init(edid->mode.pixel_clock);
if (ret)
return ret;
@@ -625,7 +625,7 @@ static int hdmi_setup(const struct edid *edid)
hdmi_audio_fifo_reset();
hdmi_audio_set_format();
- hdmi_audio_set_samplerate(edid->pixel_clock);
+ hdmi_audio_set_samplerate(edid->mode.pixel_clock);
hdmi_video_packetize();
hdmi_video_csc();
diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/rk3288/vop.c
index 30b73c2..784c6c7 100644
--- a/src/soc/rockchip/rk3288/vop.c
+++ b/src/soc/rockchip/rk3288/vop.c
@@ -39,12 +39,12 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid)
{
u32 lb_mode;
u32 rgb_mode;
- u32 hactive = edid->ha;
- u32 vactive = edid->va;
- u32 hsync_len = edid->hspw;
- u32 hback_porch = edid->hbl - edid->hso - edid->hspw;
- u32 vsync_len = edid->vspw;
- u32 vback_porch = edid->vbl - edid->vso - edid->vspw;
+ u32 hactive = edid->mode.ha;
+ u32 vactive = edid->mode.va;
+ u32 hsync_len = edid->mode.hspw;
+ u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw;
+ u32 vsync_len = edid->mode.vspw;
+ u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
u32 xpos = 0, ypos = 0;
struct rk3288_vop_regs *preg = vop_regs[vop_id];
@@ -98,14 +98,14 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid)
void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode)
{
- u32 hactive = edid->ha;
- u32 vactive = edid->va;
- u32 hfront_porch = edid->hso;
- u32 hsync_len = edid->hspw;
- u32 hback_porch = edid->hbl - edid->hso - edid->hspw;
- u32 vfront_porch = edid->vso;
- u32 vsync_len = edid->vspw;
- u32 vback_porch = edid->vbl - edid->vso - edid->vspw;
+ u32 hactive = edid->mode.ha;
+ u32 vactive = edid->mode.va;
+ u32 hfront_porch = edid->mode.hso;
+ u32 hsync_len = edid->mode.hspw;
+ u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw;
+ u32 vfront_porch = edid->mode.vso;
+ u32 vsync_len = edid->mode.vspw;
+ u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
struct rk3288_vop_regs *preg = vop_regs[vop_id];
switch (mode) {
@@ -125,8 +125,8 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode)
clrsetbits_le32(&preg->dsp_ctrl0,
M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
V_DSP_OUT_MODE(15) |
- V_DSP_HSYNC_POL(edid->phsync == '+') |
- V_DSP_VSYNC_POL(edid->pvsync == '+'));
+ V_DSP_HSYNC_POL(edid->mode.phsync == '+') |
+ V_DSP_VSYNC_POL(edid->mode.pvsync == '+'));
write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) |
V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch));
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