[coreboot-gerrit] Patch set updated for coreboot: t210: Pass in required BL31 parameters

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11382

-gerrit

commit 3fc82e61d99d8cbaeb9822b9fdd37a5728ad3838
Author: Furquan Shaikh <furquan at google.com>
Date:   Wed Aug 5 17:05:26 2015 -0700

    t210: Pass in required BL31 parameters
    
    BUG=chrome-os-partner:42989
    BRANCH=None
    TEST=Compiles successfully and boots to kernel prompt.
    
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: ff42f0b4e7f81ea97e571ec03adac16b412e4a37
    Original-Change-Id: If78857abfb9a348433b8707e58bea1f58416d243
    Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/291021
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    Original-Trybot-Ready: Furquan Shaikh <furquan at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    Original-(cherry picked from commit 68eeb4bb4b817184eb42f4ee3a840317ede07dae)
    Original-Reviewed-on: https://chromium-review.googlesource.com/290988
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    
    Change-Id: Id555198bc8e5d77f8ceee710d1a432516bd1ae4c
---
 src/soc/nvidia/tegra210/Makefile.inc |  1 +
 src/soc/nvidia/tegra210/arm_tf.c     | 47 ++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)

diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc
index 2d5bf58..0593f06 100644
--- a/src/soc/nvidia/tegra210/Makefile.inc
+++ b/src/soc/nvidia/tegra210/Makefile.inc
@@ -75,6 +75,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi-phy.c
 ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += ./jdi_25x18_display/panel-jdi-lpm102a188a.c
 ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += dp.c
 ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += sor.c
+ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c
 
 ramstage-y += sdram_lp0.c
 ramstage-y += soc.c
diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c
new file mode 100644
index 0000000..56aa4ac
--- /dev/null
+++ b/src/soc/nvidia/tegra210/arm_tf.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cache.h>
+#include <arm_tf.h>
+#include <assert.h>
+#include <soc/addressmap.h>
+#include <stdlib.h>
+#include <string.h>
+#include <symbols.h>
+
+typedef struct bl31_plat_params {
+	uint32_t tzdram_size;
+} bl31_plat_params_t;
+
+static bl31_plat_params_t t210_plat_params;
+
+void *soc_get_bl31_plat_params(bl31_params_t *params)
+{
+	uintptr_t tz_base_mib;
+	size_t tz_size_mib;
+
+	carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
+
+	assert(tz_size_mib < 4096);
+	t210_plat_params.tzdram_size = tz_size_mib * MiB;
+
+	dcache_clean_by_mva(&t210_plat_params, sizeof(t210_plat_params));
+
+	return &t210_plat_params;
+}