[coreboot-gerrit] Patch merged into coreboot/master: rockchip: rk3288: multiple NPLL rate in pll_para_config

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 8c3ab6a5f1e36ddf2c22abacee47afaddd7d0bb8
Author: Yakir Yang <ykk at rock-chips.com>
Date:   Mon Jul 27 08:50:36 2015 -0500

    rockchip: rk3288: multiple NPLL rate in pll_para_config
    
    Due to HDMI need to set dclk_rate to 27Mhz, and we can't
    caclu a suitable config paramters for this rate, so we
    need to multiple rate unless the vco larger then VCO_MAX.
    
    When NPLL rate multiple to 54MHz, pll_para_config could
    caclu a right paramters, and I have verify the clock jitter
    is okay to HDMI output.
    
    Jitter Reports:
    Dclk Rate      NPLL Rate      nr/no/nf      jitter      Margin
    27MHz          54MHz          2/10/45       449.0ps     +51.0%
    
    BRANCH=None
    BUG=chrome-os-partner:42946
    TEST=Mickey board, show right recovery picture on TV,
         and 480p clock jitter test passed
    
    Change-Id: Iaa0a6622e63d88918ed465900e630bdf16fde706
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: 59f1552026889f61167cfeaec3def668ba709c10
    Original-Signed-off-by: Yakir Yang <ykk at rock-chips.com>
    Original-Change-Id: Iab274b41f163d2d61332df13e5091f0b605cb65c
    Original-Reviewed-on: https://chromium-review.googlesource.com/288416
    Original-Commit-Queue: David Hendricks <dhendrix at chromium.org>
    Original-Tested-by: David Hendricks <dhendrix at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/290331
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Reviewed-on: http://review.coreboot.org/11393
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/11393 for details.

-gerrit