[coreboot-gerrit] Patch set updated for coreboot: intel/skylake: Force full memory train if RMT is enabled

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11414

-gerrit

commit 29a879fd428a5584db5745d4e415add7a40b91eb
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Aug 17 18:10:54 2015 -0700

    intel/skylake: Force full memory train if RMT is enabled
    
    RMT is useless if the memory does not do a full training pass,
    and since FSP does not seem to handle that case itself have
    coreboot not pass in a valid set of saved training data so FSP
    will do a full memory train.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=build and boot twice on glados with p2 and RMT enabled
    and see it do a full memory train on each boot.
    
    Change-Id: Ia4f29a937e726a5a676f056ce8970086988da5b6
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: f01e99204409899d4adbaebbe221b0348975cfa6
    Original-Change-Id: I0bb193c5f3c9206a67315906745aad96a95b3f74
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/294067
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/romstage/romstage.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 91a496e..e9f0d42 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -103,7 +103,12 @@ void soc_memory_init_params(struct romstage_params *params,
 	upd->SataMode = config->SataMode;
 	upd->EnableTraceHub = config->EnableTraceHub;
 	upd->SaGv = config->SaGv;
-	upd->RMT = config->Rmt;
+
+	if (config->Rmt) {
+		upd->RMT = 1;
+		/* Force a full memory train if RMT is enabled */
+		params->pei_data->disable_saved_data = 1;
+	}
 }
 
 void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,