[coreboot-gerrit] Patch merged into coreboot/master: intel/skylake: Implemented generic SPI driver for ROM/RAMSTAGE access.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d92f6127e109e5bb595b6726a9f7adb61eac2d9d
Author: Subrata <subrata.banik at intel.com>
Date:   Tue Jul 14 16:46:40 2015 +0530

    intel/skylake: Implemented generic SPI driver for ROM/RAMSTAGE access.
    
    Created generic library to implement SPI read, write, erase and
    read status functionality for both ROMSTAGE and RAMSTAGE access.
    
    BRANCH=NONE
    BUG=chrome-os-partner:42115
    TEST=Built for sklrvp and kunimitsu and verify SPI read, write,
    erase success from ELOG.
    
    Change-Id: Idf4ffdb550e2a3b87059554e8825a1182b448a8a
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: 74907352931db78802298fe7280a39913a37f0c2
    Original-Change-Id: Ib08da1b8825e2e88641acbac3863b926ec48afd9
    Original-Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/294444
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Tested-by: Subrata Banik <subrata.banik at intel.com>
    Original-Commit-Queue: Subrata Banik <subrata.banik at intel.com>
    Reviewed-on: http://review.coreboot.org/11422
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11422 for details.

-gerrit