[coreboot-gerrit] Patch merged into coreboot/master: intel/skylake: Add support for DPTF

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit a0f515354be6b852eea9e4dfcb99198523e52579
Author: Shilpa Sreeramalu <shilpa.sreeramalu at intel.com>
Date:   Mon Jun 22 21:48:39 2015 +0530

    intel/skylake: Add support for DPTF
    
    This patch adds the ASL files with the DPTF related settings and the
    thermal devices enabled in the SOC. It also enables the DPTF setting
    at the global NVS level.
    
    BRANCH=None
    BUG=chrome-os-partner:40855
    TEST=Built for kunimitsu board. Tested to see that the thermal devices
    and the participants are enumerated and can be seen in the
    /sys/bus/platform/devices. Also checked the temperature readings of the
    cooling devices and the thermal zones enumerated in the /sys/class/thermal.
    
    Change-Id: I8ad044eaf1ad488fb1682097da83b40d2bede414
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: 7624eeca19b4f286b30c3d4ac5b44c5e9619c2c7
    Original-Change-Id: I0d92ef42cff5567ea6fc566730588802d8549ce0
    Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/293391
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch at intel.com>
    Reviewed-on: http://review.coreboot.org/11430
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11430 for details.

-gerrit