[coreboot-gerrit] New patch to review for coreboot: UNTESTED: drivers/intel/fsp1_1: Do no run microcode updates via FSP

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11463

-gerrit

commit f8b3cbfb4284fa5a867533cfc04e1b78e46956e8
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Sat Aug 29 14:34:25 2015 -0700

    UNTESTED: drivers/intel/fsp1_1: Do no run microcode updates via FSP
    
    Our bootblock already upgrades the CPU microcode before any call to
    FSP. As a result, the FSP microcode update will be a no-op.
    THIS IS TRUE FOR THE BSP. UNTESTED ON APs.
    
    Since we have to pass the microcode location to FSP via a stack,
    before CAR, this stack exists in flash, and needs the location
    hardcoded. If we remove this limitation, then we no longer need to
    hardcode the location of the microcode, and can use the standard
    rules for adding microcode.
    
    DO NOT MERGE: THIS HAS NOT BEEN TESTED ON REAL HARDWARE.
    
    FSP DOCUMENTATION SAYS IT WILL NOT UPGRADE MICROCODE IF A VALID
    MICROCODE UPDATE IS NOT FOUND, BUT IT IS UNCLEAR IF THE FSP
    TempRamInit WILL FAIL OR NOT UNDER THESE CONDITIONS.
    
    NEEDSTEST.
    
    NOTFORMERGE!!!!
    
    Change-Id: I47d11061a1cfb741a633102225b63715d1bfd382
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/drivers/intel/fsp1_1/Kconfig              | 13 -------------
 src/drivers/intel/fsp1_1/cache_as_ram.inc     |  4 ++--
 src/soc/intel/braswell/microcode/Makefile.inc | 11 -----------
 src/soc/intel/skylake/microcode/Makefile.inc  | 11 -----------
 4 files changed, 2 insertions(+), 37 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 42c42c0..af5920b 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -45,19 +45,6 @@ config HAVE_FSP_BIN
 
 if HAVE_FSP_BIN
 
-config CPU_MICROCODE_CBFS_LEN
-	hex "Microcode update region length in bytes"
-	default 0
-	help
-	  The length in bytes of the microcode update region.
-
-config CPU_MICROCODE_CBFS_LOC
-	hex "Microcode update base address in CBFS"
-	default 0
-	help
-	  The location (base address) in CBFS that contains the microcode update
-	  binary.
-
 config FSP_FILE
 	string "Intel FSP binary path and filename"
 	help
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 6af30ce..1d35b14 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -344,8 +344,8 @@ fake_fsp_stack:
 	.long	find_fsp_ret
 
 CAR_init_params:
-	.long	CONFIG_CPU_MICROCODE_CBFS_LOC		/* Microcode Location */
-	.long	CONFIG_CPU_MICROCODE_CBFS_LEN		/* Microcode Length */
+	.long	0					/* Microcode Location */
+	.long	0					/* Microcode Length */
 	.long	0xFFFFFFFF - CONFIG_CBFS_SIZE + 1	/* Firmware Location */
 	.long	CONFIG_CBFS_SIZE				/* Total Firmware Length */
 
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
index da25b8b..3497328 100644
--- a/src/soc/intel/braswell/microcode/Makefile.inc
+++ b/src/soc/intel/braswell/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-y += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-
diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc
index a5e8981..ba308f6 100644
--- a/src/soc/intel/skylake/microcode/Makefile.inc
+++ b/src/soc/intel/skylake/microcode/Makefile.inc
@@ -1,13 +1,2 @@
 # Add CPU uCode source to list of files to build.
 cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-
-# This section overrides the default build process for the microcode to place
-# it at a known location in the CBFS.  This only needs to be enabled if FSP is
-# being used.
-# Define the correct offset for the file in CBFS
-fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC)
-
-# Override the location that was supplied by the core code.
-add-cpu-microcode-to-cbfs = \
-	$(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base)
-