[coreboot-gerrit] New patch to review for coreboot: mediatek/mt8173: Add PMIC wrapper driver
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Dec 1 19:57:24 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12589
-gerrit
commit f63174be68ed910f5a62899d28043c0d3dc90e04
Author: henryc.chen <henryc.chen at mediatek.com>
Date: Fri Jul 31 17:10:52 2015 +0800
mediatek/mt8173: Add PMIC wrapper driver
BUG=none
TEST=emerge-oak coreboot
BRANCH=none
Change-Id: Id1e9244e33e34c2c30d7c87cc277ecb7524dfb09
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: b21abfdaac4eeb2b65d4c0269ca0b9beff4b5e2f
Original-Change-Id: I84de32de3a09e7857b0695759b49d4db5fde87ec
Original-Signed-off-by: henryc.chen <henryc.chen at mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292668
Original-Commit-Ready: Julius Werner <jwerner at chromium.org>
Original-Tested-by: Yidi Lin <yidi.lin at mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
src/soc/mediatek/mt8173/Makefile.inc | 2 +
src/soc/mediatek/mt8173/include/soc/pmic_wrap.h | 255 ++++++++++++
src/soc/mediatek/mt8173/pmic_wrap.c | 493 ++++++++++++++++++++++++
3 files changed, 750 insertions(+)
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index 0d7957e..54b04bd 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -28,6 +28,8 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
+bootblock-y += pmic_wrap.c
+
################################################################################
romstage-y += cbfs.c
diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h
new file mode 100644
index 0000000..82ff07c
--- /dev/null
+++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h
@@ -0,0 +1,255 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SOC_MEDIATEK_MT8173_PMIC_WRAP_H
+#define SOC_MEDIATEK_MT8173_PMIC_WRAP_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+/* external API */
+s32 pwrap_read(u16 adr, u16 *rdata);
+s32 pwrap_write(u16 adr, u16 wdata);
+s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check);
+s32 pwrap_init(void);
+
+static struct mt8173_pwrap_regs * const mt8173_pwrap = (void *)PMIC_WRAP_BASE;
+
+enum {
+ WACS2 = 1 << 4
+};
+
+enum {
+ DEW_BASE = 0xBC00
+};
+
+/* PMIC registers */
+enum {
+ PMIC_BASE = 0x0000,
+ PMIC_WRP_CKPDN = PMIC_BASE + 0x011A, // 0x0056
+ PMIC_WRP_RST_CON = PMIC_BASE + 0x0120, // 0x005C
+ PMIC_TOP_CKCON2 = PMIC_BASE + 0x012A,
+ PMIC_TOP_CKCON3 = PMIC_BASE + 0x01D4
+};
+
+/* timeout setting */
+enum {
+ TIMEOUT_READ_US = 255,
+ TIMEOUT_WAIT_IDLE_US = 255
+};
+
+/* PMIC_WRAP registers */
+struct mt8173_pwrap_regs {
+ u32 mux_sel;
+ u32 wrap_en;
+ u32 dio_en;
+ u32 sidly;
+ u32 rddmy;
+ u32 si_ck_con;
+ u32 cshext_write;
+ u32 cshext_read;
+ u32 cslext_start;
+ u32 cslext_end;
+ u32 staupd_prd;
+ u32 staupd_grpen;
+ u32 reserved[4];
+ u32 staupd_man_trig;
+ u32 staupd_sta;
+ u32 wrap_sta;
+ u32 harb_init;
+ u32 harb_hprio;
+ u32 hiprio_arb_en;
+ u32 harb_sta0;
+ u32 harb_sta1;
+ u32 man_en;
+ u32 man_cmd;
+ u32 man_rdata;
+ u32 man_vldclr;
+ u32 wacs0_en;
+ u32 init_done0;
+ u32 wacs0_cmd;
+ u32 wacs0_rdata;
+ u32 wacs0_vldclr;
+ u32 wacs1_en;
+ u32 init_done1;
+ u32 wacs1_cmd;
+ u32 wacs1_rdata;
+ u32 wacs1_vldclr;
+ u32 wacs2_en;
+ u32 init_done2;
+ u32 wacs2_cmd;
+ u32 wacs2_rdata;
+ u32 wacs2_vldclr;
+ u32 int_en;
+ u32 int_flg_raw;
+ u32 int_flg;
+ u32 int_clr;
+ u32 sig_adr;
+ u32 sig_mode;
+ u32 sig_value;
+ u32 sig_errval;
+ u32 crc_en;
+ u32 timer_en;
+ u32 timer_sta;
+ u32 wdt_unit;
+ u32 wdt_src_en;
+ u32 wdt_flg;
+ u32 debug_int_sel;
+ u32 dvfs_adr0;
+ u32 dvfs_wdata0;
+ u32 dvfs_adr1;
+ u32 dvfs_wdata1;
+ u32 dvfs_adr2;
+ u32 dvfs_wdata2;
+ u32 dvfs_adr3;
+ u32 dvfs_wdata3;
+ u32 dvfs_adr4;
+ u32 dvfs_wdata4;
+ u32 dvfs_adr5;
+ u32 dvfs_wdata5;
+ u32 dvfs_adr6;
+ u32 dvfs_wdata6;
+ u32 dvfs_adr7;
+ u32 dvfs_wdata7;
+ u32 spminf_sta;
+ u32 cipher_key_sel;
+ u32 cipher_iv_sel;
+ u32 cipher_en;
+ u32 cipher_rdy;
+ u32 cipher_mode;
+ u32 cipher_swrst;
+ u32 dcm_en;
+ u32 dcm_dbc_prd;
+};
+
+check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148);
+
+enum {
+ RDATA_WACS_RDATA_SHIFT = 0,
+ RDATA_WACS_FSM_SHIFT = 16,
+ RDATA_WACS_REQ_SHIFT = 19,
+ RDATA_SYNC_IDLE_SHIFT,
+ RDATA_INIT_DONE_SHIFT,
+ RDATA_SYS_IDLE_SHIFT,
+};
+
+enum {
+ RDATA_WACS_RDATA_MASK = 0xffff,
+ RDATA_WACS_FSM_MASK = 0x7,
+ RDATA_WACS_REQ_MASK = 0x1,
+ RDATA_SYNC_IDLE_MASK = 0x1,
+ RDATA_INIT_DONE_MASK = 0x1,
+ RDATA_SYS_IDLE_MASK = 0x1,
+};
+
+/* WACS_FSM */
+enum {
+ WACS_FSM_IDLE = 0x00,
+ WACS_FSM_REQ = 0x02,
+ WACS_FSM_WFDLE = 0x04, /* wait for dle, wait for read data done */
+ WACS_FSM_WFVLDCLR = 0x06, /* finish read data, wait for valid flag
+ * clearing */
+ WACS_INIT_DONE = 0x01,
+ WACS_SYNC_IDLE = 0x01,
+ WACS_SYNC_BUSY = 0x00
+};
+
+/* dewrapper regsister */
+enum {
+ DEW_EVENT_OUT_EN = DEW_BASE + 0x0,
+ DEW_DIO_EN = DEW_BASE + 0x2,
+ DEW_EVENT_SRC_EN = DEW_BASE + 0x4,
+ DEW_EVENT_SRC = DEW_BASE + 0x6,
+ DEW_EVENT_FLAG = DEW_BASE + 0x8,
+ DEW_READ_TEST = DEW_BASE + 0xA,
+ DEW_WRITE_TEST = DEW_BASE + 0xC,
+ DEW_CRC_EN = DEW_BASE + 0xE,
+ DEW_CRC_VAL = DEW_BASE + 0x10,
+ DEW_MON_GRP_SEL = DEW_BASE + 0x12,
+ DEW_MON_FLAG_SEL = DEW_BASE + 0x14,
+ DEW_EVENT_TEST = DEW_BASE + 0x16,
+ DEW_CIPHER_KEY_SEL = DEW_BASE + 0x18,
+ DEW_CIPHER_IV_SEL = DEW_BASE + 0x1A,
+ DEW_CIPHER_LOAD = DEW_BASE + 0x1C,
+ DEW_CIPHER_START = DEW_BASE + 0x1E,
+ DEW_CIPHER_RDY = DEW_BASE + 0x20,
+ DEW_CIPHER_MODE = DEW_BASE + 0x22,
+ DEW_CIPHER_SWRST = DEW_BASE + 0x24,
+ DEW_CIPHER_IV0 = DEW_BASE + 0x26,
+ DEW_CIPHER_IV1 = DEW_BASE + 0x28,
+ DEW_CIPHER_IV2 = DEW_BASE + 0x2A,
+ DEW_CIPHER_IV3 = DEW_BASE + 0x2C,
+ DEW_CIPHER_IV4 = DEW_BASE + 0x2E,
+ DEW_CIPHER_IV5 = DEW_BASE + 0x30
+};
+
+/* dewrapper defaule value */
+enum {
+ DEFAULT_VALUE_READ_TEST = 0x5aa5,
+ WRITE_TEST_VALUE = 0xa55a
+};
+
+enum pmic_regck {
+ REG_CLOCK_18MHZ,
+ REG_CLOCK_26MHZ,
+ REG_CLOCK_SAFE_MODE
+};
+
+/* manual commnd */
+enum {
+ OP_WR = 0x1,
+ OP_CSH = 0x0,
+ OP_CSL = 0x1,
+ OP_OUTS = 0x8,
+ OP_OUTD = 0x9,
+ OP_INS = 0xC,
+ OP_IND = 0xD
+};
+
+/* error information flag */
+enum {
+ E_PWR_INVALID_ARG = 1,
+ E_PWR_INVALID_RW = 2,
+ E_PWR_INVALID_ADDR = 3,
+ E_PWR_INVALID_WDAT = 4,
+ E_PWR_INVALID_OP_MANUAL = 5,
+ E_PWR_NOT_IDLE_STATE = 6,
+ E_PWR_NOT_INIT_DONE = 7,
+ E_PWR_NOT_INIT_DONE_READ = 8,
+ E_PWR_WAIT_IDLE_TIMEOUT = 9,
+ E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
+ E_PWR_INIT_SIDLY_FAIL = 11,
+ E_PWR_RESET_TIMEOUT = 12,
+ E_PWR_TIMEOUT = 13,
+ E_PWR_INIT_RESET_SPI = 20,
+ E_PWR_INIT_SIDLY = 21,
+ E_PWR_INIT_REG_CLOCK = 22,
+ E_PWR_INIT_ENABLE_PMIC = 23,
+ E_PWR_INIT_DIO = 24,
+ E_PWR_INIT_CIPHER = 25,
+ E_PWR_INIT_WRITE_TEST = 26,
+ E_PWR_INIT_ENABLE_CRC = 27,
+ E_PWR_INIT_ENABLE_DEWRAP = 28,
+ E_PWR_INIT_ENABLE_EVENT = 29,
+ E_PWR_READ_TEST_FAIL = 30,
+ E_PWR_WRITE_TEST_FAIL = 31,
+ E_PWR_SWITCH_DIO = 32
+};
+
+#endif /* SOC_MEDIATEK_MT8173_PMIC_WRAP_H */
diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c
new file mode 100644
index 0000000..412eae5
--- /dev/null
+++ b/src/soc/mediatek/mt8173/pmic_wrap.c
@@ -0,0 +1,493 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <assert.h>
+#include <console/console.h>
+#include <delay.h>
+#include <soc/infracfg.h>
+#include <soc/pmic_wrap.h>
+#include <timer.h>
+
+#define PWRAPTAG "[PWRAP] "
+#define pwrap_log(fmt, arg ...) printk(BIOS_INFO, PWRAPTAG fmt, ## arg)
+#define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \
+ __LINE__, ## arg)
+
+/* define macro and inline function (for do while loop) */
+
+typedef u32 (*loop_condition_fp)(u32);
+
+static inline u32 wait_for_fsm_vldclr(u32 x)
+{
+ return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
+ WACS_FSM_WFVLDCLR;
+}
+
+static inline u32 wait_for_sync(u32 x)
+{
+ return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) !=
+ WACS_SYNC_IDLE;
+}
+
+static inline u32 wait_for_idle_and_sync(u32 x)
+{
+ return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
+ WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) &
+ RDATA_SYNC_IDLE_MASK)!= WACS_SYNC_IDLE));
+}
+
+static inline u32 wait_for_cipher_ready(u32 x)
+{
+ return x != 3;
+}
+
+static inline u32 wait_for_state_idle(u32 timeout_us, void *wacs_register,
+ void *wacs_vldclr_register,
+ u32 *read_reg)
+{
+ u32 reg_rdata;
+
+ struct stopwatch sw;
+
+ stopwatch_init_usecs_expire(&sw, timeout_us);
+ do {
+ reg_rdata = read32((wacs_register));
+ /* if last read command timeout,clear vldclr bit
+ read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
+ write:FSM_REQ-->idle */
+ switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) &
+ RDATA_WACS_FSM_MASK)) {
+ case WACS_FSM_WFVLDCLR:
+ write32(wacs_vldclr_register, 1);
+ pwrap_err("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n");
+ break;
+ case WACS_FSM_WFDLE:
+ pwrap_err("WACS_FSM = WACS_FSM_WFDLE\n");
+ break;
+ case WACS_FSM_REQ:
+ pwrap_err("WACS_FSM = WACS_FSM_REQ\n");
+ break;
+ default:
+ break;
+ }
+
+ if (stopwatch_expired(&sw))
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+
+ } while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) !=
+ WACS_FSM_IDLE); /* IDLE State */
+ if (read_reg)
+ *read_reg = reg_rdata;
+ return 0;
+}
+
+static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us,
+ void *wacs_register, u32 *read_reg)
+{
+ u32 reg_rdata;
+ struct stopwatch sw;
+
+ stopwatch_init_usecs_expire(&sw, timeout_us);
+ do {
+ reg_rdata = read32((wacs_register));
+
+ if (stopwatch_expired(&sw)) {
+ pwrap_err("timeout when waiting for idle\n");
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+ } while (fp(reg_rdata)); /* IDLE State */
+ if (read_reg)
+ *read_reg = reg_rdata;
+ return 0;
+}
+
+s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check)
+{
+ u32 reg_rdata = 0;
+ u32 wacs_write = 0;
+ u32 wacs_adr = 0;
+ u32 wacs_cmd = 0;
+ u32 return_value = 0;
+
+ if (init_check) {
+ reg_rdata = read32(&mt8173_pwrap->wacs2_rdata);
+ /* Prevent someone to used pwrap before pwrap init */
+ if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) &
+ RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) {
+ pwrap_err("initialization isn't finished \n");
+ return E_PWR_NOT_INIT_DONE;
+ }
+ }
+ reg_rdata = 0;
+ /* Check IDLE in advance */
+ return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE_US,
+ &mt8173_pwrap->wacs2_rdata,
+ &mt8173_pwrap->wacs2_vldclr,
+ 0);
+ if (return_value != 0) {
+ pwrap_err("wait_for_fsm_idle fail,return_value=%d\n",
+ return_value);
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+ wacs_write = write << 31;
+ wacs_adr = (adr >> 1) << 16;
+ wacs_cmd = wacs_write | wacs_adr | wdata;
+
+ write32(&mt8173_pwrap->wacs2_cmd, wacs_cmd);
+ if (write == 0) {
+ if (NULL == rdata) {
+ pwrap_err("rdata is a NULL pointer\n");
+ return E_PWR_INVALID_ARG;
+ }
+ return_value = wait_for_state_ready(wait_for_fsm_vldclr,
+ TIMEOUT_READ_US,
+ &mt8173_pwrap->wacs2_rdata,
+ ®_rdata);
+ if (return_value != 0) {
+ pwrap_err("wait_for_fsm_vldclr fail,return_value=%d\n",
+ return_value);
+ return E_PWR_WAIT_IDLE_TIMEOUT_READ;
+ }
+ *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT)
+ & RDATA_WACS_RDATA_MASK);
+ write32(&mt8173_pwrap->wacs2_vldclr, 1);
+ }
+
+ return 0;
+}
+
+/* external API for pmic_wrap user */
+
+s32 pwrap_read(u16 adr, u16 *rdata)
+{
+ return pwrap_wacs2(0, adr, 0, rdata, 1);
+}
+
+s32 pwrap_write(u16 adr, u16 wdata)
+{
+ return pwrap_wacs2(1, adr, wdata, 0, 1);
+}
+
+static s32 pwrap_read_nochk(u16 adr, u16 *rdata)
+{
+ return pwrap_wacs2(0, adr, 0, rdata, 0);
+}
+
+static s32 pwrap_write_nochk(u16 adr, u16 wdata)
+{
+ return pwrap_wacs2(1, adr, wdata, 0, 0);
+}
+
+/* call it in pwrap_init,mustn't check init done */
+static s32 pwrap_init_dio(u32 dio_en)
+{
+ u16 rdata = 0;
+ u32 return_value = 0;
+
+ pwrap_write_nochk(DEW_DIO_EN, dio_en);
+
+ /* Check IDLE in advance */
+ return_value =
+ wait_for_state_ready(wait_for_idle_and_sync,
+ TIMEOUT_WAIT_IDLE_US,
+ &mt8173_pwrap->wacs2_rdata,
+ 0);
+ if (return_value != 0) {
+ pwrap_err("%s fail,return_value=%#x\n", __func__, return_value);
+ return return_value;
+ }
+ write32(&mt8173_pwrap->dio_en, dio_en);
+ /* Read Test */
+ pwrap_read_nochk(DEW_READ_TEST, &rdata);
+ if (rdata != DEFAULT_VALUE_READ_TEST) {
+ pwrap_err("fail,dio_en = %#x, READ_TEST rdata=%#x\n", dio_en,
+ rdata);
+ return E_PWR_READ_TEST_FAIL;
+ }
+
+ return 0;
+}
+
+/*
+ * pwrap_init_sidly - configure serial input delay
+ *
+ * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
+ * delay. Do a read test with all possible values and chose the best delay.
+ */
+static s32 pwrap_init_sidly(void)
+{
+ u16 rdata;
+ u32 i;
+ u32 pass = 0;
+ u32 sidly = 0;
+
+ for (i = 0; i < 4; i++) {
+ write32(&mt8173_pwrap->sidly, i);
+ pwrap_wacs2(0, DEW_READ_TEST, 0, &rdata, 0);
+ if (rdata == DEFAULT_VALUE_READ_TEST)
+ pass |= 1 << i;
+ }
+
+ /*
+ * Config SIDLY according to results
+ * Pass range should be continuously or return failed
+ */
+ switch (pass) {
+ /* only 1 pass, choose it */
+ case 1 << 0:
+ sidly = 0;
+ break;
+ case 1 << 1:
+ sidly = 1;
+ break;
+ case 1 << 2:
+ sidly = 2;
+ break;
+ case 1 << 3:
+ sidly = 3;
+ break;
+ /* two pass, choose the one on SIDLY boundary */
+ case (1 << 0) | (1 << 1):
+ sidly = 0;
+ break;
+ case (1 << 1) | (1 << 2): /* no boundary, choose smaller one */
+ sidly = 1;
+ break;
+ case (1 << 2) | (1 << 3):
+ sidly = 3;
+ break;
+ /* three pass, choose the middle one */
+ case (1 << 0) | (1 << 1) | (1 << 2):
+ sidly = 1;
+ break;
+ case (1 << 1) | (1 << 2) | (1 << 3):
+ sidly = 2;
+ break;
+ /* four pass, choose the smaller middle one */
+ case (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3):
+ sidly = 1;
+ break;
+ /* pass range not continuous, should not happen */
+ default:
+ die("sidly pass range not continuous\n");
+ }
+
+ write32(&mt8173_pwrap->sidly, sidly);
+
+ return 0;
+}
+
+static s32 pwrap_reset_spislv(void)
+{
+ u32 ret = 0;
+ u32 return_value = 0;
+
+ write32(&mt8173_pwrap->hiprio_arb_en, 0);
+ write32(&mt8173_pwrap->wrap_en, 0);
+ write32(&mt8173_pwrap->mux_sel, 1);
+ write32(&mt8173_pwrap->man_en, 1);
+ write32(&mt8173_pwrap->dio_en, 0);
+
+ write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8));
+ /* to reset counter */
+ write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
+ write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8));
+ /*
+ * In order to pull CSN signal to PMIC,
+ * PMIC will count it then reset spi slave
+ */
+ write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
+ write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
+ write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
+ write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8));
+
+ return_value = wait_for_state_ready(wait_for_sync,
+ TIMEOUT_WAIT_IDLE_US,
+ &mt8173_pwrap->wacs2_rdata, 0);
+ if (return_value != 0) {
+ pwrap_err("%s fail,return_value=%#x\n", __func__, return_value);
+ ret = E_PWR_TIMEOUT;
+ }
+
+ write32(&mt8173_pwrap->man_en, 0);
+ write32(&mt8173_pwrap->mux_sel, 0);
+
+ return ret;
+}
+
+static s32 pwrap_init_reg_clock(enum pmic_regck regck_sel)
+{
+ u16 wdata = 0;
+ u16 rdata = 0;
+
+ /* Set reg clk freq */
+ pwrap_read_nochk(PMIC_TOP_CKCON2, &rdata);
+
+ if (regck_sel == REG_CLOCK_18MHZ)
+ wdata = (rdata & (~(0x3 << 10))) | (0x1 << 10);
+ else
+ wdata = rdata & (~(0x3 << 10));
+
+ pwrap_write_nochk(PMIC_TOP_CKCON2, wdata);
+ pwrap_read_nochk(PMIC_TOP_CKCON2, &rdata);
+ if (rdata != wdata) {
+ pwrap_err("pwrap_init_reg_clock,rdata=%#x\n", rdata);
+ return E_PWR_INIT_REG_CLOCK;
+ }
+ /* Config SPI Waveform according to reg clk */
+ switch (regck_sel) {
+ case REG_CLOCK_18MHZ:
+ write32(&mt8173_pwrap->rddmy, 0xc);
+ write32(&mt8173_pwrap->cshext_write, 0x0);
+ write32(&mt8173_pwrap->cshext_read, 0x4);
+ write32(&mt8173_pwrap->cslext_start, 0x0);
+ write32(&mt8173_pwrap->cslext_end, 0x4);
+ break;
+ case REG_CLOCK_26MHZ:
+ write32(&mt8173_pwrap->rddmy, 0xc);
+ write32(&mt8173_pwrap->cshext_write, 0x0);
+ write32(&mt8173_pwrap->cshext_read, 0x4);
+ write32(&mt8173_pwrap->cslext_start, 0x2);
+ write32(&mt8173_pwrap->cslext_end, 0x2);
+ break;
+ default:
+ write32(&mt8173_pwrap->rddmy, 0xf);
+ write32(&mt8173_pwrap->cshext_write, 0xf);
+ write32(&mt8173_pwrap->cshext_read, 0xf);
+ write32(&mt8173_pwrap->cslext_start, 0xf);
+ write32(&mt8173_pwrap->cslext_end, 0xf);
+ break;
+ }
+
+ return 0;
+}
+
+s32 pwrap_init(void)
+{
+ s32 sub_return = 0;
+ s32 sub_return1 = 0;
+ u16 rdata = 0x0;
+
+ setbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);
+ /* add 1us delay for toggling SW reset */
+ udelay(1);
+ /* clear reset bit */
+ clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);
+
+ /* Enable DCM */
+ write32(&mt8173_pwrap->dcm_en, 3);
+ write32(&mt8173_pwrap->dcm_dbc_prd, 0);
+
+ /* Reset SPISLV */
+ sub_return = pwrap_reset_spislv();
+ if (sub_return != 0) {
+ pwrap_err("error,pwrap_reset_spislv fail,sub_return=%#x\n",
+ sub_return);
+ return E_PWR_INIT_RESET_SPI;
+ }
+ /* Enable WACS2 */
+ write32(&mt8173_pwrap->wrap_en, 1);
+ write32(&mt8173_pwrap->hiprio_arb_en, WACS2);
+ write32(&mt8173_pwrap->wacs2_en, 1);
+
+ /* SIDLY setting */
+ sub_return = pwrap_init_sidly();
+ if (sub_return != 0) {
+ pwrap_err("error,pwrap_init_sidly fail,sub_return=%#x\n",
+ sub_return);
+ return E_PWR_INIT_SIDLY;
+ }
+ /*
+ * SPI Waveform Configuration
+ * 18MHz/26MHz/safe mode/
+ */
+ sub_return = pwrap_init_reg_clock(REG_CLOCK_26MHZ);
+ if (sub_return != 0) {
+ pwrap_err("error,pwrap_init_reg_clock fail,sub_return=%#x\n",
+ sub_return);
+ return E_PWR_INIT_REG_CLOCK;
+ }
+ /*
+ * Enable PMIC
+ */
+ pwrap_read_nochk(PMIC_WRP_CKPDN, &rdata);
+ sub_return = pwrap_write_nochk(PMIC_WRP_CKPDN, rdata & 0x50);
+ /* clear dewrap reset bit */
+ sub_return1 = pwrap_write_nochk(PMIC_WRP_RST_CON, 0);
+ if ((sub_return != 0) || (sub_return1 != 0)) {
+ pwrap_err("Enable PMIC fail, sub_return=%#x sub_return1=%#x\n",
+ sub_return, sub_return1);
+ return E_PWR_INIT_ENABLE_PMIC;
+ }
+ /* Enable DIO mode */
+ sub_return = pwrap_init_dio(1);
+ if (sub_return != 0) {
+ pwrap_err("pwrap_init_dio error code=%#x, sub_return=%#x\n",
+ 0x11, sub_return);
+ return E_PWR_INIT_DIO;
+ }
+
+ /*
+ * Write test using WACS2,
+ * make sure the read/write function ready
+ */
+ sub_return = pwrap_write_nochk(DEW_WRITE_TEST, WRITE_TEST_VALUE);
+ sub_return1 = pwrap_read_nochk(DEW_WRITE_TEST, &rdata);
+ if ((rdata != WRITE_TEST_VALUE) || (sub_return != 0)
+ || (sub_return1 != 0)) {
+ pwrap_err("write error, rdata=%#x, return=%#x, return1=%#x\n",
+ rdata, sub_return, sub_return1);
+ return E_PWR_INIT_WRITE_TEST;
+ }
+
+ /* Signature Checking - Using CRC
+ * should be the last to modify WRITE_TEST
+ */
+ sub_return = pwrap_write_nochk(DEW_CRC_EN, 0x1);
+ if (sub_return != 0) {
+ pwrap_err("enable CRC fail,sub_return=%#x\n", sub_return);
+ return E_PWR_INIT_ENABLE_CRC;
+ }
+ write32(&mt8173_pwrap->crc_en, 0x1);
+ write32(&mt8173_pwrap->sig_mode, 0x0);
+ write32(&mt8173_pwrap->sig_adr, DEW_CRC_VAL);
+
+ /* PMIC_WRAP enables */
+ write32(&mt8173_pwrap->hiprio_arb_en, 0x1ff);
+ write32(&mt8173_pwrap->wacs0_en, 0x1);
+ write32(&mt8173_pwrap->wacs1_en, 0x1);
+
+ /*
+ * switch event pin from usbdl mode to normal mode for pmic interrupt,
+ * NEW at MT6397
+ */
+ pwrap_read_nochk(PMIC_TOP_CKCON3, &rdata);
+ sub_return = pwrap_write_nochk(PMIC_TOP_CKCON3, (rdata & 0x0007));
+ if (sub_return != 0)
+ pwrap_err("!!switch event pin fail,sub_return=%d\n",
+ sub_return);
+
+ /* Initialization Done */
+ write32(&mt8173_pwrap->init_done2, 0x1);
+ write32(&mt8173_pwrap->init_done0, 0x1);
+ write32(&mt8173_pwrap->init_done1, 0x1);
+
+ return 0;
+}
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