[coreboot-gerrit] New patch to review for coreboot: google/glados: Disable kepler device

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12599

-gerrit

commit df17fc4441a86f7f2e41e55898c96d32e942ac45
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Sat Nov 21 18:47:49 2015 -0800

    google/glados: Disable kepler device
    
    Disable the kepler device to save power and enable S0ix testing.
    It has been disabled in the ME image and was not working anyway..
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=build and boot on glados
    
    Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54
    Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/313827
    Original-Commit-Ready: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/devicetree.cb | 9 +++------
 src/mainboard/google/glados/gpio.h        | 4 ++--
 2 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 7e1e6c7..f6aaac3 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -43,15 +43,12 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 
-	# Enable Root port 1 and 5.
+	# Enable Root port 1.
 	register "PcieRpEnable[0]" = "1"
-	register "PcieRpEnable[4]" = "1"
 	# Enable CLKREQ#
 	register "PcieRpClkReqSupport[0]" = "1"
-	register "PcieRpClkReqSupport[4]" = "1"
-	# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
+	# RP 1 uses SRCCLKREQ1#
 	register "PcieRpClkReqNumber[0]" = "1"
-	register "PcieRpClkReqNumber[4]" = "2"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C"  # Type-C Port (board)
 	register "usb2_ports[1]" = "USB2_PORT_MAX"     # Type-C Port (flex)
@@ -106,7 +103,7 @@ chip soc/intel/skylake
 		device pci 1c.1 off end # PCI Express Port 2
 		device pci 1c.2 off end # PCI Express Port 3
 		device pci 1c.3 off end # PCI Express Port 4
-		device pci 1c.4 on  end # PCI Express Port 5
+		device pci 1c.4 off end # PCI Express Port 5
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h
index d42b711..cd7a936 100644
--- a/src/mainboard/google/glados/gpio.h
+++ b/src/mainboard/google/glados/gpio.h
@@ -115,7 +115,7 @@ static const struct pad_config gpio_table[] = {
 /* UART0_RXD */		/* GPP_C8 */
 /* UART0_TXD */		/* GPP_C9 */
 /* UART0_RTS# */	/* GPP_C10 */
-/* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
+/* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
 /* UART1_RXD */		PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
 /* UART1_TXD */		PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
 /* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
@@ -230,7 +230,7 @@ static const struct pad_config gpio_table[] = {
 /* Early pad configuration in romstage. */
 static const struct pad_config early_gpio_table[] = {
 /* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
-/* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
+/* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
 };
 
 #endif