[coreboot-gerrit] Patch set updated for coreboot: intel/littleplains: Update with recent changes to mohonpeak

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12635

-gerrit

commit f480f95fdb9a49b99ca575d60655a1d21b61c044
Author: Martin Roth <martinroth at google.com>
Date:   Thu Dec 3 14:02:16 2015 -0700

    intel/littleplains: Update with recent changes to mohonpeak
    
    - Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE.
    - Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset.
    - Remove fixed microcode location.
    
    Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86
    Signed-off-by: Martin Roth <martinroth at google.com>
---
 src/mainboard/intel/littleplains/Kconfig        | 10 +++-------
 src/mainboard/intel/littleplains/config_seabios |  5 +++++
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/intel/littleplains/Kconfig b/src/mainboard/intel/littleplains/Kconfig
index 2fc5cb1..bde944c 100644
--- a/src/mainboard/intel/littleplains/Kconfig
+++ b/src/mainboard/intel/littleplains/Kconfig
@@ -58,16 +58,12 @@ config UART_FOR_CONSOLE
 	help
 	  The Little Plains board uses COM2 (2f8) for the serial console.
 
-config SEABIOS_MALLOC_UPPERMEMORY
-	bool
-	default n
+config PAYLOAD_CONFIGFILE
+	string
+	default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
 	help
 	  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
 	  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
 	  we put the SeaBIOS buffer area down in the 0x9000 segment.
 
-config CPU_MICROCODE_CBFS_LOC
-	hex
-	default 0xfff60040
-
 endif # BOARD_INTEL_LITTLEPLAINS
diff --git a/src/mainboard/intel/littleplains/config_seabios b/src/mainboard/intel/littleplains/config_seabios
new file mode 100644
index 0000000..f688f2b
--- /dev/null
+++ b/src/mainboard/intel/littleplains/config_seabios
@@ -0,0 +1,5 @@
+#  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
+#  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
+#  we put the SeaBIOS buffer area down in the 0x9000 segment.
+
+# CONFIG_MALLOC_UPPERMEMORY is not set