[coreboot-gerrit] New patch to review for coreboot: sb/amd/sr5650: Allow resource allocator to assign bus numbers

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12673

-gerrit

commit 5e75397a6a75ca35dc03f57164711f1d1b7202c8
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Mon Dec 7 12:22:23 2015 -0600

    sb/amd/sr5650: Allow resource allocator to assign bus numbers
    
    At some point in the past disconnected PCIe bridges were completely
    disabled to work around a hang on bridge probe.  This hang was
    resolved at some point, and the disconnected PCIe bridges should
    be enabled to receive a bus number per the RPR.
    
    This resolves a slew of warnings in the Linux boot log regarding
    invalid bridge configurations for disconnected bridge devices.
    
    Change-Id: Ic26e2d62ec5ddb9f22275c2afec7d560326263c7
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/southbridge/amd/sr5650/pcie.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 762e632..e198b87 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -768,11 +768,12 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 				if (res) {
 					AtiPcieCfg.PortDetect |= 1 << port;
 				} else {
-					/* If the training failed the disable the bridge to prevent subsequent
-					 * lockup on bridge configuration register read during the PCI bus scan
+					/* Even though nothing is attached to this port
+					 * the port needs to be "enabled" to obtain
+					 * a bus number from the PCI resource allocator
 					 */
 					training_ok = 0;
-					dev->enabled = 0;
+					dev->enabled = 1;
 				}
 			}
 		}