[coreboot-gerrit] New patch to review for coreboot: sb/amd/sb700: Enable watchdog timer for OS use

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12687

-gerrit

commit cfca8a3c890e24a35ba42b94d7681012e4348f97
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Tue Dec 8 12:09:06 2015 -0600

    sb/amd/sb700: Enable watchdog timer for OS use
    
    Change-Id: Ib0281139cafe74a22a24a377b3fdec1c59e934f3
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/southbridge/amd/sb700/early_setup.c |  3 ++-
 src/southbridge/amd/sb700/sm.c          | 17 +++++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 06c6c77..3733314 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -684,7 +684,8 @@ static void sb700_pci_cfg(void)
 
 	/* SMBus Device, BDF:0-20-0 */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
-	/* Enable watchdog decode timer */
+
+	/* Enable watchdog timer decode */
 	byte = pci_read_config8(dev, 0x41);
 	byte |= (1 << 3);
 	pci_write_config8(dev, 0x41, byte);
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 04f4601..8eacb9f 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -30,6 +30,7 @@
 
 #define NMI_OFF 0
 
+#define SB_MMIO_RESOURCE_NUMBER 0x9c
 #define PRIMARY_SMBUS_RESOURCE_NUMBER 0x90
 #define AUXILIARY_SMBUS_RESOURCE_NUMBER 0x58
 
@@ -283,6 +284,13 @@ static void sm_init(device_t dev)
 
 		byte |= 1 << 3;
  		pci_write_config8(dev, 0x43, byte);
+
+		/* Enable southbridge MMIO decode */
+		dword = pci_read_config32(dev, 0x9c);
+		dword &= ~(0xffffff << 8);
+		dword |= 0xfeb00000;
+		dword |= 0x1;
+		pci_write_config32(dev, 0x9c, dword);
 	}
 	//ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER
  	byte = pci_read_config8(dev, 0xAE);
@@ -417,6 +425,15 @@ static void sb700_sm_read_resources(device_t dev)
 	res->gran = 8;
 	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
 
+	/* WDT */
+	res = new_resource(dev, SB_MMIO_RESOURCE_NUMBER);
+	res->base  = 0xfeb00000;	/* reset SB MMIO to widely accepted address */
+	res->size = 0x1000;
+	res->limit = 0xFFFFFFFFUL;	/* res->base + res->size -1; */
+	res->align = 8;
+	res->gran = 8;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
+
 	/* HPET */
 	res = new_resource(dev, 0xB4);	/* TODO: test hpet */
 	res->base  = 0xfed00000;	/* reset hpet to widely accepted address */