[coreboot-gerrit] Patch set updated for coreboot: soc/intel/fsp_baytrail: Adjust root port INT routing

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12684

-gerrit

commit 4eb086f9f385f3b3f9e133341332d6c5356d5ff2
Author: Martin Roth <martinroth at google.com>
Date:   Mon Dec 7 16:50:47 2015 -0700

    soc/intel/fsp_baytrail: Adjust root port INT routing
    
    Adjust the root port INT routing based on Bay Trail spec:
    Document Number: 538136, Rev. 3.9
    
    Table 241. Interrupt Generated for INT[A-D] Interrupts
                 INTA  INTB  INTC  INTD
    Root Port 1 INTA# INTB# INTC# INTD#
    Root Port 2 INTD# INTA# INTB# INTC#
    Root Port 3 INTC# INTD# INTA# INTB#
    Root Port 4 INTB# INTC# INTD# INTA#
    
    ACPI had the root port swizzling going in the wrong direction.
    
    This still isn't complete though, because the ACPI is still
    swizzling the root ports, which isn't correct.
    We need to see which bus is attached to which root port and
    adjust the swizzling for the bus, not the root port.
    
    Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d
    Signed-off-by: Martin Roth <martinroth at google.com>
---
 src/soc/intel/fsp_baytrail/acpi/irq_helper.h |  8 ++++----
 src/soc/intel/fsp_baytrail/southcluster.c    | 10 ++++++++++
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h
index a8cf3ef..03df177 100644
--- a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h
+++ b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h
@@ -93,13 +93,13 @@ Name(prefix_ ## func_ ## A, Package() \
 
 #define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
 	RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
-	RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 1, d_, a_, b_, c_) \
 	RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
-	RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
+	RP_IRQ_ROUTES(prefix_, 3, b_, c_, d_, a_) \
 	RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
-	RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 5, d_, a_, b_, c_) \
 	RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
-	RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
+	RP_IRQ_ROUTES(prefix_, 7, b_, c_, d_, a_)
 
 #define RP_METHOD(prefix_, dev_, func_)\
 Device(prefix_ ## 0 ## func_) \
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index 6182948..1d5bbee 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -208,6 +208,16 @@ static void write_pci_config_irqs(void)
 		if (targ_dev == NULL || new_int_pin < 1)
 			continue;
 
+		/*
+		 * Adjust the INT routing for the PCIe root ports
+		 * See 'Interrupt Generated for INT[A-D] Interrupts'
+		 * Table 241 in Document Number: 538136, Rev. 3.9
+		 */
+		if (PCI_SLOT(targ_dev->path.pci.devfn) == PCIE_DEV &&
+				targ_dev != irq_dev)
+			new_int_pin = ((new_int_pin - 1 +
+				PCI_FUNC(targ_dev->path.pci.devfn)) % 4) + 1;
+
 		/* Get the original INT_PIN for record keeping */
 		original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);