[coreboot-gerrit] New patch to review for coreboot: fsp1_1: supply fsp version to mrc_cache API

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12701

-gerrit

commit f6ba378f06d890b54949e766c8ba3118b189f4ee
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Dec 9 16:00:18 2015 -0600

    fsp1_1: supply fsp version to mrc_cache API
    
    The memory init code needs to match the saved mrc data. To
    ensure that invariant holds supply the FSP version when
    using the mrc cache API.
    
    BUG=chrome-os-partner:46050
    BRANCH=None
    TEST=Built and booted on glados. Verified version mismatch checking
         works.
    
    Change-Id: I3f6dd19cb15a18761d34509749adafc89a72ed2d
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/drivers/intel/fsp1_1/include/fsp/romstage.h |  2 +-
 src/drivers/intel/fsp1_1/include/fsp/util.h     |  7 +++++++
 src/drivers/intel/fsp1_1/romstage.c             | 14 ++++++++++----
 3 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index 7d2df7c..eddf346 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -27,7 +27,7 @@
 #include <soc/pm.h>		/* chip_power_state */
 
 struct romstage_params {
-	unsigned long bist;
+	uint32_t fsp_version;
 	struct chipset_power_state *power_state;
 	struct pei_data *pei_data;
 	void *chipset_context;
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 5595e73..07cf0c7 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -45,6 +45,13 @@ void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
 void *get_first_resource_hob(const EFI_GUID *guid);
 void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old,
 	uint64_t new);
+
+/* Return version of FSP associated with fih. */
+static inline uint32_t fsp_version(FSP_INFO_HEADER *fih)
+{
+	return fih->ImageRevision;
+}
+
 /*
  * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success.
  * The FSP source is pointed to by region_device and the relocation information
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index b50bf73..16db4df 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -62,11 +62,14 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
 	/* Display parameters */
 	printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
 		CONFIG_MMCONF_BASE_ADDRESS);
-	printk(BIOS_INFO, "Using FSP 1.1");
+	printk(BIOS_INFO, "Using FSP 1.1\n");
 
 	/* Display FSP banner */
 	print_fsp_info(fih);
 
+	/* Stash FSP version. */
+	params.fsp_version = fsp_version(fih);
+
 	/* Get power state */
 	params.power_state = fill_power_state();
 
@@ -125,7 +128,8 @@ void romstage_common(struct romstage_params *params)
 			/* Recovery mode does not use MRC cache */
 			printk(BIOS_DEBUG,
 			       "Recovery mode: not using MRC cache.\n");
-		} else if (!mrc_cache_get_current(&cache)) {
+		} else if (!mrc_cache_get_current_with_version(&cache,
+							params->fsp_version)) {
 			/* MRC cache found */
 			params->pei_data->saved_data_size = cache->size;
 			params->pei_data->saved_data = &cache->data[0];
@@ -151,8 +155,10 @@ void romstage_common(struct romstage_params *params)
 	if (params->pei_data->boot_mode != SLEEP_STATE_S3) {
 		if (params->pei_data->data_to_save_size != 0 &&
 		    params->pei_data->data_to_save != NULL) {
-			mrc_cache_stash_data(params->pei_data->data_to_save,
-				params->pei_data->data_to_save_size);
+			mrc_cache_stash_data_with_version(
+				params->pei_data->data_to_save,
+				params->pei_data->data_to_save_size,
+				params->fsp_version);
 		}
 	}