[coreboot-gerrit] New patch to review for coreboot: southbridge/amd/sb600: Update HPET base address with #define
Martin Roth (martinroth@google.com)
gerrit at coreboot.org
Thu Dec 10 16:55:52 CET 2015
Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12705
-gerrit
commit deb01ae89f75551068d7dfc57002e6500ed675e4
Author: Martin Roth <martinroth at google.com>
Date: Thu Dec 10 08:19:27 2015 -0700
southbridge/amd/sb600: Update HPET base address with #define
The SB600 code had the base address of the HPET hardcoded throughout.
It looks like the plan was to have it be updated in ACPI if needed,
but this wasn't ever implemented. The variable names being used to
do this update were the same, causing an IASL warning. Because of
this, the operation to update the HPET address actually did nothing.
This was fine, because it didn't actually need to be updated.
- Replace all that code with a #define.
- Add and update some comments in the same area.
Fixes IASL warning:
dsdt.aml 1505: Store(HPBA, HPBA)
Warning 3023 - ^ Duplicate value in list (Source is the
same as Target)
Change-Id: I9ba5fe226a4a464e0045ce7d3406898760df5e5a
Signed-off-by: Martin Roth <martinroth at google.com>
---
src/mainboard/amd/dbm690t/dsdt.asl | 13 ++++++-------
src/mainboard/amd/pistachio/dsdt.asl | 13 ++++++-------
src/mainboard/kontron/kt690/dsdt.asl | 13 ++++++-------
src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 10 ++++------
src/mainboard/technexion/tim5690/dsdt.asl | 13 ++++++-------
src/mainboard/technexion/tim8690/dsdt.asl | 13 ++++++-------
src/southbridge/amd/sb600/sb600.h | 4 ++++
src/southbridge/amd/sb600/sm.c | 2 +-
8 files changed, 39 insertions(+), 42 deletions(-)
diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl
index 46d3671..744c687 100644
--- a/src/mainboard/amd/dbm690t/dsdt.asl
+++ b/src/mainboard/amd/dbm690t/dsdt.asl
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <southbridge/amd/sb600/sb600.h>
+
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1361,20 +1362,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPTM) {
+ Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {
diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl
index 6322289..0e8bd05 100644
--- a/src/mainboard/amd/pistachio/dsdt.asl
+++ b/src/mainboard/amd/pistachio/dsdt.asl
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <southbridge/amd/sb600/sb600.h>
+
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1360,20 +1361,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPTM) {
+ Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {
diff --git a/src/mainboard/kontron/kt690/dsdt.asl b/src/mainboard/kontron/kt690/dsdt.asl
index 5884e74..05b6855 100644
--- a/src/mainboard/kontron/kt690/dsdt.asl
+++ b/src/mainboard/kontron/kt690/dsdt.asl
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <southbridge/amd/sb600/sb600.h>
+
/* DefinitionBlock Statement */
DefinitionBlock (
"dsdt.aml", /* Output filename */
@@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1362,20 +1363,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPTM) {
+ Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {
diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
index 699bb93..3d85966 100644
--- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
+++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
@@ -16,13 +16,13 @@
*/
#include <arch/ioapic.h>
#include <cpu/x86/lapic_def.h>
+#include <southbridge/amd/sb600/sb600.h>
DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
{
/* Data to be patched by the BIOS during POST */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
@@ -1004,17 +1004,15 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPET) {
+ Device(HPET) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
}
diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl
index a763bcf..14d0bfa 100644
--- a/src/mainboard/technexion/tim5690/dsdt.asl
+++ b/src/mainboard/technexion/tim5690/dsdt.asl
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <southbridge/amd/sb600/sb600.h>
+
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1361,20 +1362,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPTM) {
+ Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {
diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl
index 692c02b..e831750 100644
--- a/src/mainboard/technexion/tim8690/dsdt.asl
+++ b/src/mainboard/technexion/tim8690/dsdt.asl
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include <southbridge/amd/sb600/sb600.h>
+
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
@@ -33,7 +35,6 @@ DefinitionBlock (
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
- Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1361,20 +1362,18 @@ DefinitionBlock (
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
- Device(HPTM) {
+ Device(HPTM) { /* HPET */
Name(_HID,EISAID("PNP0103"))
Name(CRS,ResourceTemplate() {
- Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x00000400, HPT) /* 1kb reserved space */
})
Method(_STA, 0) {
- Return(0x0F) /* sata is visible */
+ Return(0x0F) /* HPET is visible */
}
Method(_CRS, 0) {
- CreateDwordField(CRS, ^HPT._BAS, HPBA)
- Store(HPBA, HPBA)
Return(CRS)
}
- } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.HPTM) */
} /* end LIBR */
Device(HPBR) {
diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h
index 93671fa..c707324 100644
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -25,6 +25,9 @@
#define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1
+#define HPET_BASE_ADDRESS 0xfed00000
+
+#ifndef __ACPI__
extern void pm_iowrite(u8 reg, u8 value);
extern u8 pm_ioread(u8 reg);
extern void pm2_iowrite(u8 reg, u8 value);
@@ -36,4 +39,5 @@ void sb600_enable(device_t dev);
void sb600_lpc_port80(void);
void sb600_pci_port80(void);
+#endif /* __ACPI__ */
#endif /* SB600_H */
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index 8cfd358..5773ae2 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -305,7 +305,7 @@ static void sb600_sm_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
res = new_resource(dev, 0x14); /* hpet */
- res->base = 0xfed00000; /* reset hpet to widely accepted address */
+ res->base = HPET_BASE_ADDRESS; /* reset hpet to widely accepted address */
res->size = 0x400;
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
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