[coreboot-gerrit] Patch set updated for coreboot: gigabyte/ga-g41m-es2l: Add mainboard
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Mon Dec 14 12:58:44 CET 2015
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11306
-gerrit
commit 393b94694ce5ffa710ec902f9fdea17a47d5cb78
Author: Damien Zammit <damien at zamaudio.com>
Date: Wed Aug 19 15:23:32 2015 +1000
gigabyte/ga-g41m-es2l: Add mainboard
Board uses x4x native raminit
Board boots to linux with a small patch to prog_loaders.c
(ignoring EARLY_CBMEM), also using "noapic" linux kernel option.
Change-Id: I7417813456817529b8cbaace45cefe47467d0a82
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 53 +++++++
src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name | 2 +
src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc | 1 +
src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl | 1 +
.../gigabyte/ga-g41m-es2l/acpi/gm45_pci_irqs.asl | 68 +++++++++
.../gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl | 34 +++++
.../gigabyte/ga-g41m-es2l/acpi/superio.asl | 1 +
src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c | 32 +++++
src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt | 5 +
src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 37 +++++
src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 99 +++++++++++++
src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl | 41 ++++++
src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c | 7 +
src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 154 +++++++++++++++++++++
14 files changed, 535 insertions(+)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
new file mode 100644
index 0000000..29d65c9
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
@@ -0,0 +1,53 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_GIGABYTE_GA_G41M_ES2L
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA775
+ select NORTHBRIDGE_INTEL_X4X
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_ITE_IT8718F
+ select HAVE_ACPI_TABLES
+ select EARLY_CBMEM_INIT
+ select BOARD_ROMSIZE_KB_1024
+
+config IASL_WARNINGS_ARE_ERRORS
+ bool
+ default n
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xe0000000
+
+# First 0x100 bytes of rom is protected,
+# cant be flashed in-place with external programmer.
+# So shrink CBFS to not go there.
+config CBFS_SIZE
+ hex "Size of CBFS filesystem in ROM"
+ default 0xFFF00
+
+
+config MAINBOARD_DIR
+ string
+ default gigabyte/ga-g41m-es2l
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "GA-G41M-ES2L"
+
+endif # BOARD_GIGABYTE_GA_G41M_ES2L
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name
new file mode 100644
index 0000000..e685ce1
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GIGABYTE_GA_G41M_ES2L
+ bool "GA-G41M-ES2L"
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc
new file mode 100644
index 0000000..f9621db
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc
@@ -0,0 +1 @@
+ramstage-y += cstates.c
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/gm45_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/gm45_pci_irqs.asl
new file mode 100644
index 0000000..8dfeec9
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/gm45_pci_irqs.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for x4x */
+
+/* PCI Interrupt Routing */
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ /* High Definition Audio 0:1b.0 */
+ Package() { 0x001bffff, 0, 0, 22 },
+ /* PCIe Root Ports 0:1c.x */
+ Package() { 0x001cffff, 0, 0, 16 },
+ Package() { 0x001cffff, 1, 0, 17 },
+ Package() { 0x001cffff, 2, 0, 18 },
+ Package() { 0x001cffff, 3, 0, 19 },
+ /* USB and EHCI 0:1d.x */
+ Package() { 0x001dffff, 0, 0, 23 },
+ Package() { 0x001dffff, 1, 0, 19 },
+ Package() { 0x001dffff, 2, 0, 18 },
+ Package() { 0x001dffff, 3, 0, 16 },
+ Package() { 0x001dffff, 0, 0, 23 },
+ /* PCI 0:1e.0 */
+ Package() { 0x001effff, 0, 0, 17 },
+ Package() { 0x001effff, 1, 0, 20 },
+ /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */
+ Package() { 0x001fffff, 1, 0, 19 },
+ Package() { 0x001fffff, 1, 0, 19 },
+ Package() { 0x001fffff, 0, 0, 18 },
+ })
+ } Else {
+ Return (Package() {
+ /* High Definition Audio 0:1b.0 */
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ /* PCIe Root Ports 0:1c.x */
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ /* USB and EHCI 0:1d.x */
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+ /* PCI 0:1e.0 */
+ Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..2e3f1b7
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 17},
+ Package() { 0x0000ffff, 1, 0, 20},
+ Package() { 0x0000ffff, 2, 0, 16},
+ Package() { 0x0000ffff, 3, 0, 16},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+ })
+}
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c
new file mode 100644
index 0000000..677ebcf
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <arch/ioapic.h>
+
+#include "southbridge/intel/i82801gx/nvs.h"
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+}
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt
new file mode 100644
index 0000000..44ed73a
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt
@@ -0,0 +1,5 @@
+Category: desktop
+Board URL:
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c
new file mode 100644
index 0000000..dbac2ed
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+
+static acpi_cstate_t cst_entries[] = {
+ {
+ /* acpi C1 / cpu C1 */
+ 1, 0x01, 1000,
+ { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
+ },
+ {
+ /* acpi C2 / cpu C2 */
+ 2, 0x01, 500,
+ { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
+ },
+};
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
new file mode 100644
index 0000000..e86910e
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
@@ -0,0 +1,99 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/x4x # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x # CPU
+ register "slfm" = "1"
+ register "c5" = "1"
+ register "c6" = "1"
+ end
+ end
+ device domain 0 on # PCI domain
+ device pci 0.0 on end # Host Bridge
+ device pci 1.0 off end # PCI Bridge to Management Engine
+ device pci 2.0 off end # Integrated graphics controller
+ device pci 3.0 off end # ME
+ device pci 3.1 off end # ME
+ chip southbridge/intel/i82801gx # Southbridge
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x0b"
+ register "pirqc_routing" = "0x0b"
+ register "pirqd_routing" = "0x0b"
+ register "pirqe_routing" = "0x0b"
+ register "pirqf_routing" = "0x0b"
+ register "pirqg_routing" = "0x0b"
+ register "pirqh_routing" = "0x0b"
+ register "ide_legacy_combined" = "0x1"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x0"
+
+ device pci 1b.0 on end # Audio
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on end # PCIe 2
+ device pci 1d.0 on end # USB
+ device pci 1d.1 on end # USB
+ device pci 1d.2 on end # USB
+ device pci 1d.3 on end # USB
+ device pci 1d.7 on end # USB
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA bridge
+ chip superio/ite/it8718f # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ drq 0x74 = 0
+ drq 0x75 = 0
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 4
+ end
+ device pnp 2e.4 on # Environment controller
+ io 0x60 = 0x290
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off end # Mouse
+ device pnp 2e.7 off end # GPIO
+ end
+ end
+ device pci 1f.1 off end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMbus
+ device pci 1f.4 off end
+ device pci 1f.5 off end
+ device pci 1f.6 off end
+ end
+ end
+end
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl
new file mode 100644
index 0000000..bb7aa51
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20090419 // OEM revision
+)
+{
+ // Some generic macros
+ //#include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/x4x/acpi/gm45.asl>
+ #include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c
new file mode 100644
index 0000000..072a306
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c
@@ -0,0 +1,7 @@
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[0] = {};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
new file mode 100644
index 0000000..fc17eca
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <northbridge/intel/x4x/x4x.h>
+#include <cpu/x86/bist.h>
+#include <superio/ite/it8718f/it8718f.h>
+#include <superio/ite/common/ite.h>
+#include <lib.h>
+#include <cpu/intel/romstage.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
+#define SUPERIO_DEV PNP_DEV(0x2e, 0)
+
+/* Early mainboard specific GPIO setup.
+ * We should use standard gpio.h eventually
+ */
+
+static void mb_gpio_init(void)
+{
+ device_t dev;
+
+ /* Southbridge GPIOs. */
+ dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+ /* Set the value for GPIO base address register and enable GPIO. */
+ pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
+ pci_write_config8(dev, GPIO_CNTL, 0x10);
+
+ outl(0x1f15f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+ outl(0xe2e9ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+ outl(0xe0d7fcc3, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+ outl(0x000000e7, DEFAULT_GPIOBASE + 0x30);
+ outl(0x000000f0, DEFAULT_GPIOBASE + 0x34);
+ outl(0x00000083, DEFAULT_GPIOBASE + 0x38);
+
+ /* Set default power management registers */
+ pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1);
+ outw(0x0011, DEFAULT_PMBASE + 0x00);
+ outw(0x0120, DEFAULT_PMBASE + 0x02);
+ outl(0x00001c01, DEFAULT_PMBASE + 0x04);
+ outl(0x00bb29d2, DEFAULT_PMBASE + 0x08);
+ outl(0x000000a0, DEFAULT_PMBASE + 0x10);
+ outl(0xc5000000, DEFAULT_PMBASE + 0x28);
+ outl(0x00000040, DEFAULT_PMBASE + 0x2c);
+ outw(0x13e0, DEFAULT_PMBASE + 0x44);
+ outw(0x003f, DEFAULT_PMBASE + 0x60);
+ outw(0x0800, DEFAULT_PMBASE + 0x68);
+ outw(0x0008, DEFAULT_PMBASE + 0x6a);
+ outw(0x003f, DEFAULT_PMBASE + 0x72);
+
+ /* Set default GPIOs on superio */
+ ite_reg_write(GPIO_DEV, 0x25, 0x00);
+ ite_reg_write(GPIO_DEV, 0x26, 0xc7);
+ ite_reg_write(GPIO_DEV, 0x27, 0x80);
+ ite_reg_write(GPIO_DEV, 0x28, 0x41);
+ ite_reg_write(GPIO_DEV, 0x29, 0x0a);
+ ite_reg_write(GPIO_DEV, 0x2c, 0x01);
+ ite_reg_write(GPIO_DEV, 0x62, 0x08);
+ ite_reg_write(GPIO_DEV, 0x62, 0x08);
+ ite_reg_write(GPIO_DEV, 0x72, 0x00);
+ ite_reg_write(GPIO_DEV, 0x73, 0x00);
+ ite_reg_write(GPIO_DEV, 0xbb, 0x40);
+ ite_reg_write(GPIO_DEV, 0xc0, 0x00);
+ ite_reg_write(GPIO_DEV, 0xc1, 0xc7);
+ ite_reg_write(GPIO_DEV, 0xc2, 0x80);
+ ite_reg_write(GPIO_DEV, 0xc3, 0x01);
+ ite_reg_write(GPIO_DEV, 0xc4, 0x0a);
+ ite_reg_write(GPIO_DEV, 0xc8, 0x00);
+ ite_reg_write(GPIO_DEV, 0xc9, 0x04);
+ ite_reg_write(GPIO_DEV, 0xcb, 0x00);
+ ite_reg_write(GPIO_DEV, 0xcc, 0x02);
+ ite_reg_write(GPIO_DEV, 0xf0, 0x10);
+ ite_reg_write(GPIO_DEV, 0xf1, 0x40);
+ ite_reg_write(GPIO_DEV, 0xf6, 0x26);
+ ite_reg_write(GPIO_DEV, 0xfc, 0x52);
+
+ /* IRQ routing */
+ RCBA32(0x3100) = 0x00002210;
+ RCBA32(0x3104) = 0x00002100;
+ RCBA32(0x3108) = 0x10004321;
+ RCBA32(0x310c) = 0x00214321;
+ RCBA32(0x3110) = 0x00000001;
+ RCBA32(0x3140) = 0x00410032;
+ RCBA32(0x3144) = 0x32100237;
+}
+
+static void ich7_enable_lpc(void)
+{
+ /* Disable Serial IRQ */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00);
+ /* Decode range */
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
+ CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
+
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);
+}
+
+void main(unsigned long bist)
+{
+ // ch0 ch1
+ const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
+
+ /* Disable watchdog timer and route port 80 to LPC */
+ RCBA32(0x3410) = (RCBA32(0x3410) | 0x20);// & ~0x4;
+
+ /* Set southbridge and Super I/O GPIOs. */
+ mb_gpio_init();
+
+ ich7_enable_lpc();
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ /* Disable SIO reboot */
+ ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
+
+ console_init();
+
+ report_bist_failure(bist);
+ enable_smbus();
+
+ x4x_early_init();
+
+ printk(BIOS_DEBUG, "Initializing memory\n");
+ sdram_initialize(0, spd_addrmap);
+ quick_ram_check();
+ printk(BIOS_DEBUG, "Memory initialized\n");
+
+ cbmem_initialize_empty();
+}
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