[coreboot-gerrit] New patch to review for coreboot: intel/skylake: Work around ROMCC optimization bug

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12719

-gerrit

commit 297a244c33198453354f54280785405541925d4a
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Mon Dec 14 15:53:21 2015 -0800

    intel/skylake: Work around ROMCC optimization bug
    
    On Skylake systems, the bootblock fails to compile with the following
    error message:
    
    bootblock_simple.c:6.1:
    0x13930e0 copy       Internal compiler error: non dominated rhs use point
    0x13a3f70?
    Aborted (core dumped)
    
    The option -fno-simplify-phi works around the issue, but will cause the
    code to use more registers, hence we also need to enable -mcpu=p4 (see
    intel/truxton mainboard for another example of where this has been done
    in the past)
    
    Change-Id: Iea1a1ba18d76c7323bb626c5f4b0032e4ee04a86
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 src/soc/intel/skylake/Makefile.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index e824f2a..9dd4cac 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -78,4 +78,6 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
 # Currently used for microcode path.
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
+ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2
+
 endif