[coreboot-gerrit] New patch to review for coreboot: BCRD2: Fix leakage on V1P8S rail

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12730

-gerrit

commit 537171f71757f5565b465a75c000cb841bd48bd4
Author: Shobhit Srivastava <shobhit.srivastava at intel.com>
Date:   Mon Aug 10 11:48:23 2015 +0530

    BCRD2: Fix leakage on V1P8S rail
    
    This patch fixes the leakage seen on V1P8S rail on BCRD2 boards.
    Leakage was caused due to MMC1_RCLK GPIO. Tri stating this GPIO
    fixes the issue.
    
    Reviewed-on: https://chromium-review.googlesource.com/292043
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Commit-Queue: Divagar Mohandass <divagar.mohandass at intel.com>
    Tested-by: Divagar Mohandass <divagar.mohandass at intel.com>
    
    Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c
    Signed-off-by: Shobhit Srivastava <shobhit.srivastava at intel.com>
---
 src/soc/intel/braswell/include/soc/gpio.h | 1 +
 src/soc/intel/braswell/smihandler.c       | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index 08cfd0c..d58b44d 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -104,6 +104,7 @@
 #define MMC1_D5_MMIO_OFFSET		GPIO_OFFSET(65)
 #define MMC1_D6_MMIO_OFFSET		GPIO_OFFSET(63)
 #define MMC1_D7_MMIO_OFFSET		GPIO_OFFSET(68)
+#define MMC1_RCLK_OFFSET		GPIO_OFFSET(69)
 #define HV_DDI2_DDC_SDA_MMIO_OFFSET	GPIO_OFFSET(62)
 #define HV_DDI2_DDC_SCL_MMIO_OFFSET	GPIO_OFFSET(67)
 #define CFIO_139_MMIO_OFFSET		GPIO_OFFSET(64)
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index b637420..335ede1 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -117,6 +117,8 @@ static void tristate_gpios(uint32_t val)
 			MMC1_D6_MMIO_OFFSET, val);
 	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
 			MMC1_D7_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
+			MMC1_RCLK_OFFSET, val);
 
 	/* Tri-state HDMI */
 	write32((void *)COMMUNITY_GPNORTH_BASE +