[coreboot-gerrit] New patch to review for coreboot: Strago: Enable native mode on sd card cd line
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Wed Dec 16 04:05:46 CET 2015
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12741
-gerrit
commit cc9f49d135385626502380532f9c8ebc5e8c012c
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Date: Wed Nov 4 14:25:15 2015 -0800
Strago: Enable native mode on sd card cd line
Configuring Native Mode enables the card present bit in
sd card controller register.
TEST=Sd Card Plug/Unplug should work in OS and DepthCharge.
Reviewed-on: https://chromium-review.googlesource.com/310847
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
src/mainboard/intel/strago/gpio.c | 36 ++++++++++++++-----------------
src/soc/intel/braswell/include/soc/gpio.h | 5 +++++
2 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c
old mode 100755
new mode 100644
index 8b6a0e7..a9215ab
--- a/src/mainboard/intel/strago/gpio.c
+++ b/src/mainboard/intel/strago/gpio.c
@@ -12,13 +12,15 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- */
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+*/
#include "irqroute.h"
#include <soc/gpio.h>
#include <stdlib.h>
-#include <boardid.h>
-#include "onboard.h"
#include "gpio.h"
/* South East Community */
@@ -74,7 +76,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */
- NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */
+ NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */
GPIO_NC, /* 82 spkr asummed gpio number */
Native_M1, /* 83 SUSPWRDNACK */
SPARE_PIN,/* 84 spare pin */
@@ -112,11 +114,11 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA),
/* 37 MF_HDA_DOCKENB */
NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */
- GPIO_NC, /* 46 I2C4_SDA */
+ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */
NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */
NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */
GPIO_NC, /* 49 I2C_NFC_SDA */
- GPIO_NC, /* 50 I2C4_SCL */
+ NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */
NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */
GPIO_NC, /* 52 I2C_NFC_SCL */
NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */
@@ -128,9 +130,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */
GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */
GPIO_OUT_HIGH, /* 75 SATA_GP0 */
- GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
+ GPIO_NC,
/* 76 GPI SATA_GP1 */
- Native_M1, /* 77 SATA_LEDN */
+ GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
GPIO_NC, /* 80 SATA_GP3 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
@@ -169,9 +171,11 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
/* 17 GPIO_SUS3 */
GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */
- GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */
+ GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
+ /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */
- GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA),
+ GPI(trig_edge_high, L2, P_20K_H, non_maskable,
+ en_edge_rx_data, NA , NA),
/* 21 SEC_GPIO_SUS11 */
GPIO_NC, /* 22 GPIO_SUS4 */
GPIO_NC,
@@ -242,7 +246,7 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_NC, /* 19 MF_GPIO_5 */
GPIO_NC, /* 20 MF_GPIO_9 */
GPIO_NC, /* 21 MF_GPIO_0 */
- GPIO_NC, /* 22 MF_GPIO_4 */
+ GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */
GPIO_NC, /* 23 MF_GPIO_8 */
GPIO_NC, /* 24 MF_GPIO_2 */
GPIO_NC, /* 25 MF_GPIO_6 */
@@ -261,13 +265,5 @@ static struct soc_gpio_config gpio_config = {
struct soc_gpio_config *mainboard_get_gpios(void)
{
-
- switch (board_id()) {
- case BOARD_DVT:
- return get_override_gpios_dvt();
- case BOARD_BCRD2:
- return get_override_gpios_bcrd2();
- default:
- return &gpio_config;
- }
+ return &gpio_config;
}
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index 08cfd0c..5c1d7d2 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -274,6 +274,11 @@
| PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\
.pad_conf1 = PAD_CONFIG1_DEFAULT0 }
+#define NATIVE_INT_PU20K(mode, int_sel) {\
+ .pad_conf0 = PAD_PULL_UP_20K | PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \
+ | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\
+ .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
+
#define SPEAKER \
{ .pad_conf0 = PAD_CONFIG0_DEFAULT0, \
.pad_conf1 = PAD_CONFIG1_DEFAULT0 }
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