[coreboot-gerrit] New patch to review for coreboot: imgtec/pistachio: increase CBFS cache

[Ionela Voinescu (ionela.voinescu@imgtec.com)]

Ionela Voinescu (ionela.voinescu at imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12762

-gerrit

commit c714b2db724bfc176dcd7d2a333162e1ef458fb6
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Thu Aug 6 19:22:53 2015 +0100

    imgtec/pistachio: increase CBFS cache
    
    Increase CBFS cache size to allow for a bigger payload.
    
    Change-Id: I47404ba9bbe95f6610189b971504019c0a1a81f0
    Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
---
 src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index ce0063f..edf9c41 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -26,8 +26,8 @@ SECTIONS
 	DRAM_START(0x00000000)
 	/* DMA coherent area: accessed via KSEG1. */
 	DMA_COHERENT(0x00100000, 1M)
-	POSTRAM_CBFS_CACHE(0x00200000, 192K)
-	RAMSTAGE(0x00230000, 128K)
+	POSTRAM_CBFS_CACHE(0x00200000, 512K)
+	RAMSTAGE(0x00280000, 128K)
 
 	/*
 	 * GRAM becomes the SRAM.  Accessed through KSEG0 in the bootblock