[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/urara: change SYS PLL to 700MHz

[Ionela Voinescu (ionela.voinescu@imgtec.com)]

Ionela Voinescu (ionela.voinescu at imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12765

-gerrit

commit dbbd42aeb89e3d4ae51ac9002874962cd114a0ca
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Wed Jul 15 12:10:05 2015 +0100

    mainboard/google/urara: change SYS PLL to 700MHz
    
    This requires changes the interface that sets up the system
    PLL to support a given reference devider value and given
    feedback value.
    Also, this requires a change in the dividers used for UART,
    USB, I2C setup.
    
    Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5
    Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
---
 src/mainboard/google/urara/bootblock.c        | 20 ++++++++++----------
 src/soc/imgtec/pistachio/clocks.c             | 25 +++++++++++++++++--------
 src/soc/imgtec/pistachio/include/soc/clocks.h |  2 +-
 3 files changed, 28 insertions(+), 19 deletions(-)

diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c
index 40696b6..7775916 100644
--- a/src/mainboard/google/urara/bootblock.c
+++ b/src/mainboard/google/urara/bootblock.c
@@ -172,7 +172,7 @@ static void bootblock_mainboard_init(void)
 {
 	int ret;
 
-	/* System PLL divided by 2 -> 400 MHz */
+	/* System PLL divided by 2 -> 350 MHz */
 	/* The same frequency will be the input frequency for the SPFI block */
 	system_clk_setup(1);
 
@@ -181,8 +181,8 @@ static void bootblock_mainboard_init(void)
 	 * the values set or not by the boot ROM code */
 	mips_clk_setup(0, 0);
 
-	/* Setup system PLL at 800 MHz */
-	ret = sys_pll_setup(2, 1);
+	/* Setup system PLL at 700 MHz */
+	ret = sys_pll_setup(2, 1, 13, 350);
 	if (ret != CLOCKS_OK)
 		return;
 	/* Setup MIPS PLL at 546 MHz */
@@ -193,9 +193,9 @@ static void bootblock_mainboard_init(void)
 	/* Setup SPIM1 MFIOs */
 	spim1_mfio_setup();
 	/* Setup UART1 clock and MFIOs
-	 * System PLL divided by 7 divided by 62 -> 1.8433 Mhz
+	 * System PLL divided by 5 divided by 76 -> 1.8421 Mhz
 	 */
-	uart1_clk_setup(6, 61);
+	uart1_clk_setup(4, 75);
 	uart1_mfio_setup();
 }
 
@@ -213,23 +213,23 @@ static int init_extra_hardware(void)
 	}
 
 	/* Setup USB clock
-	 * System clock divided by 8 -> 50 MHz
+	 * System clock divided by 7 -> 50 MHz
 	 */
-	if (usb_clk_setup(7, 2, 7) != CLOCKS_OK) {
+	if (usb_clk_setup(6, 2, 7) != CLOCKS_OK) {
 		printk(BIOS_ERR, "%s: Failed to set up USB clock.\n",
 			__func__);
 		return -1;
 	}
 
 	/* Setup I2C clocks and MFIOs
-	 * System PLL divided by 4 divided by 3 -> 33.33 MHz
+	 * System clock divided by 4 divided by 3 -> 29.1(6) MHz
 	 */
 	i2c_clk_setup(3, 2, hardware->i2c_interface);
 	i2c_mfio_setup(hardware->i2c_interface);
 
 	/* Ethernet clocks setup: ENET as clock source */
-	eth_clk_setup(0, 7);
-	/* ROM clock setup: system clock divided by 2 -> 200 MHz */
+	eth_clk_setup(0, 6);
+	/* ROM clock setup: system clock divided by 2 -> 175 MHz */
 	/* Hash accelerator is driven from the ROM clock */
 	rom_clk_setup(1);
 
diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c
index 40c45b0..43bdc55 100644
--- a/src/soc/imgtec/pistachio/clocks.c
+++ b/src/soc/imgtec/pistachio/clocks.c
@@ -44,6 +44,13 @@
 #define SYS_PLL_STATUS_ADDR		0xB8144038
 #define SYS_PLL_STATUS_LOCK_MASK	0x00000001
 
+#define SYS_PLL_REFDIV_ADDR		0xB814403C
+#define SYS_PLL_REFDIV_MASK		0x0000003F
+#define SYS_PLL_REFDIV_SHIFT		0
+#define SYS_PLL_FEEDBACK_ADDR		0xB814403C
+#define SYS_PLL_FEEDBACK_MASK		0x0003FFC0
+#define SYS_PLL_FEEDBACK_SHIFT		6
+
 #define MIPS_PLL_POSTDIV_ADDR		0xB8144004
 #define MIPS_PLL_POSTDIV1_MASK		0x001C0000
 #define MIPS_PLL_POSTDIV1_SHIFT		18
@@ -156,13 +163,13 @@ static struct pll_parameters pll_params[] = {
 		.status_addr = SYS_PLL_STATUS_ADDR,
 		.status_lock_mask = SYS_PLL_STATUS_LOCK_MASK,
 		.refdivider = 0, /* Not defined yet */
-		.refdiv_addr = 0, /* Not necessary */
-		.refdiv_shift = 0, /* Not necessary */
-		.refdiv_mask = 0, /* Not necessary */
-		.feedback = 0, /* Not necessary */
-		.feedback_addr = 0, /* Not necessary */
-		.feedback_shift = 0, /* Not necessary */
-		.feedback_mask = 0, /* Not necessary */
+		.refdiv_addr = SYS_PLL_REFDIV_ADDR,
+		.refdiv_shift = SYS_PLL_REFDIV_SHIFT,
+		.refdiv_mask = SYS_PLL_REFDIV_MASK,
+		.feedback = 0, /* Not defined yet */
+		.feedback_addr = SYS_PLL_FEEDBACK_ADDR,
+		.feedback_shift = SYS_PLL_FEEDBACK_SHIFT,
+		.feedback_mask = SYS_PLL_FEEDBACK_MASK
 	},
 
 	[MIPS_PLL] = {
@@ -263,8 +270,10 @@ static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2)
 	return CLOCKS_OK;
 }
 
-int sys_pll_setup(u8 divider1, u8 divider2)
+int sys_pll_setup(u8 divider1, u8 divider2, u8 refdivider, u32 feedback)
 {
+	pll_params[SYS_PLL].refdivider = refdivider;
+	pll_params[SYS_PLL].feedback = feedback;
 	return pll_setup(&(pll_params[SYS_PLL]), divider1, divider2);
 }
 
diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h
index f351a6f..fc07f0a 100644
--- a/src/soc/imgtec/pistachio/include/soc/clocks.h
+++ b/src/soc/imgtec/pistachio/include/soc/clocks.h
@@ -21,7 +21,7 @@
 #include <stdint.h>
 
 /* Functions for PLL setting */
-int sys_pll_setup(u8 divider1, u8 divider2);
+int sys_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback);
 int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback);
 
 /* Peripheral divider setting */