[coreboot-gerrit] Patch set updated for coreboot: imgtec/pistachio: identity map SOC registers region

[Ionela Voinescu (ionela.voinescu@imgtec.com)]

Ionela Voinescu (ionela.voinescu at imgtec.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12770

-gerrit

commit 6d768b0ff9bbea1e9f5263468527aff44f0a56c5
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date:   Thu Dec 17 19:16:01 2015 +0000

    imgtec/pistachio: identity map SOC registers region
    
    This region must be mapped uncached. This is necesary for an
    U-boot payload which will obtain all register base addresses
    as physical addresses from the device tree and will use them
    as such.
    
    Change-Id: Ib5041df7d90c6ef61b7448a18dd732afbd9489ca
    Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
---
 src/soc/imgtec/pistachio/bootblock.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c
index eceb814..23f6471 100644
--- a/src/soc/imgtec/pistachio/bootblock.c
+++ b/src/soc/imgtec/pistachio/bootblock.c
@@ -57,4 +57,6 @@ static void bootblock_mmu_init(void)
 	assert(!identity_map((uint32_t)_sram, _sram_size,
 						C0_ENTRYLO_COHERENCY_WB));
 	assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB));
+	assert(!identity_map((uint32_t)_soc_registers, _soc_registers_size,
+                                                C0_ENTRYLO_COHERENCY_UC));
 }